本論文提出兩種CMOS參考電壓電路。第一種電路為差動模式參考電壓；第二種電路為混合模式參考電壓。本論文提出之參考電壓電路設計原理是利用BJT電晶體所產生的溫度係數特性電壓與MOS電晶體偏壓於弱反轉區所產生的溫度係數特性電壓，以適當的權重比例相互抵消，來實現零溫度係數參考電壓。與已知的參考電壓電路相比，本論文提出之電路使用並聯電阻的方式來調控電流，進而提升零溫度係數參考電壓的穩定性，此外不需要使用運算放大器可以減少抵補電壓產生的誤差。

本論文除了提供詳細的設計原理之外，使用TSMC 0.18微米製程參數以HSPICE與ADE(Analog Design Environment)電路模擬軟體針對電路進行佈局前/後模擬與晶片實作；佈局前/後模擬結果與設計理論互相符合，也證明了電路的可行性。本論文所提出之參考電壓電路可應用於各種類比、數位、以及混合模式積體電路設計。

In this thesis, two CMOS reference voltage circuits have been proposed. The first circuit is a differential-mode reference voltage and the second circuit is a mixed-mode reference voltage. In the proposed reference voltage circuits, the design theory is using the temperature-coefficient characteristic generated by the BJT and the temperature-coefficient characteristic generated by the MOSFET biased in the weak inversion region with appropriate ratios to cancel each other therefore a zero temperature-coefficient reference voltage can be achieved. Compared with the related conventional reference voltage circuits, the circuit proposed in this thesis parallel-connected resistors have been used to adjust the zero temperature-coefficient current therefore the stability of the reference voltage is enhanced. Besides, there is no operational amplifier in the proposed circuits, consequently they would not suffer from the offset voltage of the operational amplifier.

Detailed operating principles have been explored in this thesis. Both the proposed circuits have been simulated by HSPICE and ADE circuit simulation program with TSMC 0.18 um process parameters, also the proposed circuits have been tape-out. The pre and post layout simulation results are consistent with the theoretical analysis which can be used to prove the feasibility of the proposed circuits. The proposed reference voltage circuits can be used in analog, digital, and mixed-mode integrated circuit applications.

摘要.....i
Abstract.....ii
誌謝.....iii
目錄.....iv
表目錄.....vi
圖目錄.....vii
符號說明.....ix
第一章 緒論.....1
1.1研究背景與動機.....1
1.2設計流程.....1
1.3研究方向與重點.....4
1.4論文架構簡介.....4
第二章 參考電壓工作原理.....5
2.1參考電壓介紹與原理.....5
2.1.1齊納二極體參考電壓電路.....6
2.1.2 BJT參考電壓電路.....7
2.1.3 MOSFET參考電壓電路.....9
2.2弱反轉區(Weak inversion).....11
2.3負溫度係數.....12
2.4正溫度係數.....14
第三章 CMOS差動模式參考電壓分析與設計實務.....15
3.1 傳統差動模式參考電壓設計.....15
3.2 第一種差動模式參考電壓電路.....17
3.2.1第一種差動模式參考電壓電路工作原理.....18
3.2.2第一種差動模式參考電壓電路模擬結果.....19
3.2.3第一種差動模式參考電壓電路佈局圖.....21
3.3 第二種差動模式參考電壓電路.....22
3.3.1第二種差動模式參考電壓電路工作原理.....23
3.3.2第二種差動模式參考電壓電路模擬結果.....24
3.3.3第二種差動模式參考電壓電路佈局圖.....26
3.4 兩種差動模式參考電壓電路模擬結果整理與討論.....27
第四章 CMOS混合模式參考電壓分析與設計實務.....28
4.1 混合模式參考電壓設計.....28
4.2 第一種混合模式參考電壓電路.....29
4.2.1第一種混合模式參考電壓電路工作原理.....30
4.2.2第一種混合模式參考電壓電路模擬結果.....31
4.2.3第一種混合模式參考電壓電路佈局圖.....33
4.3 第二種混合模式參考電壓電路.....34
4.3.1第二種混合模式參考電壓電路工作原理.....34
4.3.2第二種混合模式參考電壓電路模擬結果.....35
4.3.3第二種混合模式參考電壓電路佈局圖.....37
4.4 兩種混合模式參考電壓電路模擬結果整理與討論.....38
第五章 晶片實作與量測結果.....39
5.1 全客製化IC設計流程.....39
5.2 量測儀器與流程.....41
5.3 第一種差動模式參考電壓電路晶片實體與量測結果.....42
5.3.1 晶片實體.....42
5.3.2晶片量測結果.....43
5.4 第二種差動模式參考電壓電路晶片實體與量測結果.....48
5.4.1 晶片實體.....48
5.4.2晶片量測結果.....49
5.5 第一種混合模式參考電壓電路晶片實體與量測結果.....54
5.5.1 晶片實體.....54
5.5.2晶片量測結果.....55
5.6 第二種混合模式參考電壓電路晶片實體與量測結果.....57
5.6.1 晶片實體.....57
5.6.2晶片量測結果.....58
第六章 結論與討論.....60
參考文獻.....61
Extended Abstract.....63

[1]Zhang Shuo,Wang Zongmin,Zhou Liang,Feng Wenxiao and Ding Yang,”A high-PSRR bandgap voltage reference with temperature curvature compensation used for pipeline ADC,” 2013 IEEE International Conference of Electron Devices and Solid-Satae Circuit(EDSSC),pp.1-2,2013.
[2]K. R. Francisco and J. A. Hora , “Very Low Bandgap Voltage Reference with High PSRR Enhancement Stage Implemented in 90nm CMOS Process Technology for LDO Application”, 2012 IEEE International Conference on Electronics Design Systems and Applications (ICEDSA), pp. 216-220, 2012.
[3]謝永瑞，2008，“VLSI概論(修訂四版)”全華科技圖書股份有限公司。
[4]高德遠、康繼昌，1992，“VLSI-系統和電路的設計原理”儒林圖書有限公司。
[5]Ge Tao, Fu Xiansong, Niu Pingjuan, Yang Guanghua, and Gao Tiecheng, “High-performance floating output bandgap circuit,” 2010 2nd International Conference on Signal Processing Systems, vol.3, pp. V3-224 – V3-226, 2010.
[6]B. Razavi, "Design of Analogue CMOS Integrated Circuits,” McCraw-Hill Companies Inc. Bostom. MA, 2001.
[7]E. Mattia, H. Klimach, and S. Bampi “0.9 V, 5 nW, 9 ppm/oC resistorless sub-bandgap voltage reference in 0.18μm CMOS,” 2014 IEEE 5th Latin American Symposium on Circuits and Systems, pp. 1 – 4, 2014.
[8]K. E. Kujik, 1973, “A Precision Reference Voltage Source,” IEEE J. of Solid-State Circuit, vol.8, pp. 222-226, June.
[9]Na Sun and R. Sobot, 2010, "A low-power low-voltage bandgap reference in CMOS," 2010 23rd Canadian Conference on Electrical and Computer Engineering, pp.1 - 5, Calgary, May.
[10]廖家正，“CMOS參考電壓設計”，國立虎尾科技大學電子工程系研究所碩士論文，2013年，7月。
[11]Min Tan, Fan Liu, and Fei Xiang, “A novel sub-1-V bandgap reference in 0.18µm CMOS technology”, 2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification, pp. 180-183, 2011.
[12]E. K. F. Lee, “A low voltage CMOS bandgap reference without using an opamp” , 2009 IEEE International Symposium on Circuits and Systems, pp. 2533-2536, 2009.
[13]G. Giustolisi, G. Palumbo, M. Criscione, and F. Cutrì, “A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs”, IEEE Journal of Solid State Circuits, vol. 38, No.1, pp. 151-154, Jan. 2003.
[14]Chia-Wei Chang, Tien-Yu Lo, Chia-Min Chen, Kuo-Hsi Wu, and Chung-Chih Hung, “A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation”, 2007 IEEE International Symposium on Circuits and Systems, pp. 3844-3847, 2007.
 
[15]Yilei Li, Yu Wang, Na Yan, Xi Tan, and Hao Min, “A subthreshold MOSFET bandgap reference with ultra-low power supply voltage”, 2011 IEEE 9th International Conference on ASIC, pp. 862-865, 2011.
[16]吳源輝，“混合模式差動輸出參考電壓設計”，國立虎尾科技大學電子工程系研究所碩士論文，2019年，7月。
[17]賴政翰，“CMOS差動模式輸出參考電壓設計實務”，國立虎尾科技大學電子工程系研究所碩士論文，2020年，7月。
[18]Marco Ferro, Franco Salerno, and Rinaldo Castello,“A Floating CMOS Bandgap Voltage Reference for Differential Applications,” Fourteenth European Solid-State Circuits Conference, pp.219 – 222, Manchester, UK,1988.September.
[19]Todd L. Brook, and Alan L. Westwick,“A Low-Power Differential CMOS Bandgap Reference,” 1994 IEEE International Solid-State Circuits Conference, pp.248 – 249, San Francisco, CA, USA, 1994.February.