臺灣博碩士論文加值系統

本論文提出具內建偏移誤差消除功能之全數位CMOS智慧型溫度感測器，採用循環式架構來增加元件使用效率來節省成本。本電路包含脈衝縮減循環延遲線電路(Pulse-Shrinking Cyclic Delay Line, PSCDL)、脈衝寬度偵測電路(Pulse Width Detecting Circuit, PWDC)以及計數器(Counter, CNT)，其中PSCDL內建控制單元、脈衝縮減單元(Pulse Shrinking Unit, PSU)、溫度感測延遲線(Temperature-Sensing Delay Line, TSDL)以及時間增加延遲線(Time-Added Delay Line, TADL)，首先，TSDL用來產生溫度感測脈衝，而PSU則實現脈衝縮減功能，此外，內建於PSCDL內之TADL則用來產生時間增加脈衝，其結合 PWDC可實現內建偏移誤差消除；最後，利用CNT計數脈衝縮減次數並輸出數位值以達成溫度轉換數位值功能。本感測器以TSMC 0.35-μm CMOS製程實作，晶片面積為 0.023 mm2，其溫度解析度約為0.1 °C/LSB，而誤差在-20 ~ 60°C之溫度範圍內僅為 ± 0.3 °C。

An all-digital CMOS smart temperature sensor with build-in offset-error cancellation is presented. The cyclic structure increases the efficiency of the used element for cost saving. The proposed sensor consists of a pulse-shrinking cyclic delay line (PSCDL), a pulse width detecting circuit (PWDC), and a counter (CNT). The PSCDL contains two control units, a pulse-shrinking unit (PSU), a temperature-sensing delay line (TSDL), and a time-added delay line (TADL). First, the TSDL is used to generate a temperature-sensing pulse. Then, the PSU is adopted for the pulse-shrinking function. Additionally, the TADL in the PSCDL is used to create a time-added pulse, combining the PWDC to perform the build-in offset-error cancellation. Finally, the CNT is used to count the times of pulse-shrinking number for output coding. The sensor was fabricated with TSMC 0.35-μm CMOS process and had a small area of 0.023 mm2. The measured temperature resolution reaches about 0.1 °C/LSB, and the corresponding error is merely ±0.3 °C in a range of -20 ~ 60 °C.

摘要 I
ABSTRACT II
誌謝 III
目錄 III
表目錄 VI
圖目錄 VII
一、 緒論 1
1.1 研究動機 1
1.2 論文架構 4
二、 智慧型溫度感測器探討 5
2.1 智慧型溫度感測器介紹 5
2.1.1 積體電路(半導體)溫度感測器 6
2.1.2 熱敏電容溫度感測器 6
2.1.3 熱電耦溫度感測器(Thermocouple,TC) 7
2.1.4 電阻式溫度感測器(Resistance Temperature Detector,RTD) 7
2.1.5 溫度感測器之整理與比較 8
2.2 積體電路式之時域型溫度感測器 9
2.2.1 時域脈衝循環式溫度感測器(一) 10
2.2.2 時域脈衝循環式溫度感測器(二) 11
三、 全數位CMOS具內建偏移誤差消除功能之智慧型溫度感測器 12
3.1 研究目的 12
3.2 整體電路架構 13
3.3 脈衝縮減循環延遲線 (PSCDL) 15
3.3.1 內建於循環圈之脈衝產生器 16
3.3.2 時間扣抵機制 18
3.3.3 溫度感測延遲線(TSDL) 19
3.3.4 全數位MOS電容機制 21
3.4 為解決偏移誤差問題所提出之新穎的時間增加偵測電路 24
3.4.1 本論文使用之脈衝寬度偵測電路(PWDC) 26
3.5 脈衝中和技術 27
3.5.1 控制單元之脈衝中和 29
3.5.2 訊號分流處之脈衝中和 30
四、 電路設計與模擬 32
4.1 設計流程與規格考量 32
4.2 脈衝縮減循環延遲線電路模擬 35
4.3 全數位MOS電容機制之脈衝縮減單元模擬 36
4.4 溫度感測器模擬 37
4.5 脈衝中和技術模擬 38
4.6 脈衝寬度偵測電路模擬 39
五、 量測結果、結論與未來展望 40
5.1 量測環境設定 40
5.2 量測步驟與結果 42
5.3 結論 47
5.4 問題與討論 48
參考文獻 49

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