臺灣博碩士論文加值系統

本論文針對
5G NR-LDPC矩陣設計解碼器， 5G NR針對不同碼字長度定 義了八種
不同矩陣，環境越好可以使用越高的編碼率，不同編碼率 可以透過將矩陣等比例縮小來
完成，但縮小矩陣必須改變硬體架構，應對不同編碼率需要不同硬體架構來應對，但會
付出巨大的硬體面積，在不改變硬體架構的情況下，採用在接收端補 0的方式運算便能
達到相同的解碼效能。解碼演算法採用最小和演算法 ，解碼器 輸入資料 為 LLR型式，輸
入資料 量化 為 6位元 ，一組完整的輸入資料有 816筆，連續進入 的情況下 需要兩塊記憶
體交換儲存， 迭代次數 為 八次 一次迭代運算需要 70個時脈，記憶體採用只儲存每列的
最小值、第二小值、符號、最小值位置，這樣只需在運算時將符號與大小做結合在做運
算，但在運算過程必須等到所 有行都計 算完成才能將值更新，所以使用兩塊交換儲存，
雖然運算時間長卻能 大幅 減少 記憶體面積 。 使用 TSMC 18um製成實現晶片，晶片的工
作頻率為 40MHz、功率消耗為 308.6659mW、晶片面積為 7.5704×7.5602 mm2。

This paper designs a decoder for the 5G NR-LDPC matrix. 5G NR defines eight different matrices for different codeword lengths. The better the environment, the higher the coding rate can be used. Different coding rates can be achieved by reducing the matrix in equal proportions. However, to reduce the matrix, the hardware architecture must be changed. Different encoding rates require different hardware architectures, but a huge hardware area will be paid. Without changing the hardware architecture, it is easy to calculate by adding 0 at the receiving end. can achieve the same decoding performance. The decoding algorithm adopts the minimum sum algorithm. The input data of the decoder is LLR type, and the input data is quantized into 6 bits. There are 816 complete sets of input data. In the case of continuous input, two memory blocks are required for exchange and storage, and the number of iterations It takes 70 clocks for eight iterations, and the memory only stores the minimum value, second minimum value, symbol, and minimum value position of each column, so that only the symbol and the size need to be combined in the operation. However, in the operation process, the value must be updated until all rows are calculated, so using two blocks of exchange storage, although the operation time is long, it can reduce the memory area, and the operation is completed using a hard decision output. The realization chip is made of TSMC 18um, the operating frequency of the chip is 40MHz, the power consumption is 308.6659mW, and the chip area is 7.5704×7.5602 mm2.

摘要......i
Abstract......ii
誌謝......iii
目錄......iv
表目錄......vii
圖目錄......viii
第一章 緒論......1
1.1 研究動機......1
1.2 研究目的......2
1.3 研究方法......3
1.4 論文架構......4
第二章 相關背景......5
2.1 線性區塊碼......5
2.2 低密度同位元檢查碼......6
2.3 Tanner圖......7
2.4 QC-LDPC......8
2.5 對數似然比......10
2.5.1 二位元相位偏移調變......11
2.5.2 四位元相位偏移調變......12
2.5.3 16正交振幅調變......13
2.5.4 64正交振幅調變......18
第三章 NR-LDPC編解碼演算法與硬體架構......22
3.1 編碼演算法......22
3.2 解碼演算法......24
3.2.1 和積演算法......24
3.2.2 最小和演算法......26
3.2.3 正規化最小和演算法......28
3.3 模擬分析......29
3.3.1 不同演算法效能模擬......29
3.3.2 矩陣效能分析......30
3.3.3 不同編碼率模擬......31
3.3.4 位元長度分析......33
3.3.5 迭代次數......34
3.4 硬體架構......35
3.4.1 記憶體......35
3.4.2 全並行......36
3.4.3 列並行......37
3.4.4 行並行......39
第四章 實驗設計與結果......41
4.1 解碼器架構......41
4.2.1 Control Unit......42
4.2.1 Initial Register......44
4.2.2 H Register......45
4.2.3 Register Output Control Unit......46
4.2.4 Shifter......47
4.2.5 VNU......51
4.2.5.1 Clipping......53
4.2.5.2 Sigma Clipping......54
4.2.6 CNU......55
4.2.7 Hard Decision......56
4.2 測試結果......57
4.3 晶片實作......60
第五章 結論......63
參考文獻......64
附錄一......67
Extended Abstract......69

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