臺灣博碩士論文加值系統

本論文研究了三種低電壓矽積體電路頻率信號源的電路性能和工作原理，使用
台積電 0.18μm BiCMOS 工藝製作。
第一個電路是一個除 4 和除 8 注入鎖定除頻器。除 8 除頻器在功耗為 9.2 mW
下的鎖定範圍為 2.6 GHz，從 14.6 GHz 到 17.2 GHz。此電路使用一個除 2 環形
振盪器除頻器並聯一個用作除 2 或者除 4 的電容性交叉耦合振盪器。另外，此電
路使用了不平衡電路參數以降低功耗並保留差分輸出。第二個電路是一個除 4 和
除 8 注入鎖定除頻器。本電路使用平衡的電路參數並提供四個正交輸出。除 8 除
頻器在功耗為 6.6 mW 下的鎖定範圍為 1.16 GHz，從 11.6 GHz 至 12.29 GHz。
兩種 2:1 除頻器都是使用具有注入電壓控制電阻器的新注入技術來降低工作電
壓。第三個電路是 D 類的零臨限值電晶體無變容諧振器壓控振盪器。D 類壓控振
盪器輸出擺幅約為電源電壓的 3 倍。在 0.3 V 的電源電壓下，其核心功耗為 3mW。
通過改變電源電壓，可將振盪頻率從 2.74GHz 調節到 2.62GHz。低功耗工作模式
可經由降低電源電壓獲得。將零臨限值電晶體電壓振盪器與電荷泵電路結合在一
起可設計出一種有用的能量收集電路。
關鍵字：除頻器，鎖定範圍，差分和正交除 8 注入鎖定除頻器，混頻器，電壓
控制振盪器，零臨限值電壓互補性氧化金屬半導體電晶體。

This thesis studies the circuit performance and working principles of three low-voltage frequency
signal sources in the TSMC 0.18 μm 1P6M BiCMOS process.
The first circuit is about a CMOS divide-by-4 and -8 injection-locked frequency divider (ILFD)
with a divide-by-2 ring-oscillator-based frequency divider (FD) in shunt with an LC-tank capacitive
cross-coupled divide-by-2 or -4 ILFD. The ILFD has a 4:1 locking range 4.7 GHz from 4.5 GHz to 9.2
GHz while the power consumption is 7.67 mW. At an external injected signal power Pinj of 0 dBm, the
integrated ILFD has an 8:1 locking range 2.6 GHz from 14.6 GHz to 17.2 GHz at the power consumption
of 9.2 mW. The divide-by-4 and -8 ILFD uses the varactor-less 2:1 oscillator FD with wide locking range
to follow the input frequency signal supplied by the LC ILFD. The 2:1 FD has four outputs and is
designed with a schematic with unbalanced parameter values. The unbalanced circuit reduces the power
consumption and preserves the differential outputs.
The second circuit is about a divide-by-8 ILFD with a 2:1 oscillator FD in parallel with an LC
divide-by-4 ILFD. The ILFD provides four quadrature outputs. The divide-by-8 ILFD owns a measured
locking range 1.16 GHz from 11.13 GHz to 12.29 GHz while it consumes 6.6 mW. Both 2:1 ringoscillator-based FDs use a new injection technique with injection-voltage-controlled resistors to reduce
the voltage headroom.
The third circuit is about a class-D varactor-free LC-resonator voltage-controlled-oscillator (VCO).
The VCO output swing is about 3 times of supply voltage. When the supply voltage biased at 0.3 V , the
power consumption of VCO-core is 3mW. The oscillation frequency is changeable from 2.74GHz to
2.62GHz by varying the supply voltage. By lowering the supply voltage, we can operate the VCO at lowpower mode. By combing a zero-VTH MOSFET oscillator with a charge pump circuit, we can design a
useful energy harvesting circuit.
Keywords: Frequency divider, current-mode logic, locking range, differential and quadrature divide-by8 injection-locked frequency dividers, mixer, voltage-controlled-oscillators, zero-threshold voltage
MOSFET.

Table of Contents
摘要........................................................................................................................... I
ABSTRACT.............................................................................................................. II
誌謝......................................................................................................................... III
CATALOG ............................................................................................................... IV
LIST OF TABLES..................................................................................................... V
LIST OF FIGURES.................................................................................................. VI
CHAPTER 1 INTRODUCTION ............................................................................. 10
1.1 RESEARCH BACKGROUND ............................................................................... 10
1.2 RESEARCH MOTIVATION AND OBJECTIVE......................................................... 15
1.3 ORGANIZATION OF THE THESIS ........................................................................ 16
CHAPTER 2 EVEN-MODULUS INJECTION-LOCKED FREQUENCY DIVIDER
USING SHUNT UNBALANCED 2:1 FREQUENCY DIVIDER ............................ 20
2.1 INTRODUCTION ............................................................................................... 20
2.2 CIRCUIT DESIGN ............................................................................................. 20
2.3 MEASUREMENT OF THE DIVIDE-BY-4/8 ILFD................................................... 25
CHAPTER 3 QUADRATURE DIVISION-BY-8 FREQUENCY DIVIDER
PERFORMED WITH INJECTION-VOLTAGE CONTROLLED RESISTOR......... 31
3.1 INTRODUCTION ............................................................................................... 31
3.2 DESIGN OF QUADRATURE ÷8 FREQUENCY DIVIDER.......................................... 32
3.3 EXPERIMENTAL DIVIDE-BY-8 ILFD................................................................. 39
3.4 THEORY OF RING OSCILLATOR ........................................................................ 40
3.5 DIVIDE-BY-4 RING OSCILLATOR ...................................................................... 43
CHAPTER 4 CLASS-D LC OSCILLATOR USING ZERO-THRESHOLD
VOLTAGE MOSFET .............................................................................................. 45
4.1 CLASS OF OSCILLATOR.................................................................................... 46
4.2 OSCILLATOR CIRCUIT DESIGN ......................................................................... 48
4.3 MEASUREMENT RESULTS ................................................................................ 53
4.4 DC-DC CONVERTER....................................................................................... 53
CHAPTER 5 CONCLUSION.................................................................................. 57
REFERENCES........................................................................................................ 58V
List of Tables
Table 2-1 Performance Comparison of CMOS ÷8 and ÷4 LC ILFDs........................ 29
Table 3-1 Performance Comparison of Simulated ÷4/8 QILFDs .............................. 36
Table 3-2 Design Parameters of Simulated ÷4 LC ILFDs......................................... 36VI
List of Figures
Fig. 1-1. (a) Block diagram of divide-by-2 counter and its waveform. (b) Divide-by-8
counter. ................................................................................................................... 10
Fig. 1-2. (a) Block diagram of a PLL with shunt TSPC, CML and ILFD...................11
Fig. 1-2. (b) RF receiver architecture with a ÷8 quadrature FD. ................................11
Fig. 1-2. (c) Frequency divider chain used to characterize the high frequency VCO
with lower frequency set-up. ....................................................................................11
Fig. 1-3. (a) Block diagram of the ÷2/4 FD.. ............................................................ 12
Fig. 1-3. (b) Schematic of the ÷2 LC-tank ILFD. ..................................................... 12
Fig. 1-3. (c) Diagram of injection locking sensitivity. .............................................. 12
Fig. 1-4(a). Divide-by-8 FD [1]. .............................................................................. 13
Fig. 1-4(b). Measured TSPC divide-by-8 output. (a) Input waveform and (b) output
waveform. ............................................................................................................... 13
Fig. 1-5. (a) Feedback oscillator model and (b) negative-resistance oscillator model.
(c) Oscillator............................................................................................................ 14
Fig. 1-6. Typical spectrum of oscillator.................................................................... 15
Fig. 1-7. Block diagram of divide-by-4 FDs with two sub-FDs................................ 16
Fig. 1-8. (a) Block diagrams of differential oscillator and quadrature oscillator. (b)
Block diagram of frequency divider. (c) Block diagram of divide-by-4 quadrature FD..
................................................................................................................................ 17
Fig. 1-9. (a) Cross-section of a normal threshold voltage MOSFET. (b) Cross-section
of a zero-threshold voltage MOSFET....................................................................... 18
Fig. 1-10. Transfer I-V characteristics of native and conventional nMOSFETs. VDD=
0.1V. W/L=0.25/0.3μm............................................................................................ 18
Fig. 2-1 (a) Schematic of the studied ÷4/8 ILFD using shunt ILFDs. (b) Stand-alone
CML FD.................................................................................................................. 21VII
Fig. 2-2. (a) Simulated CML voltage waveforms.(b) Simulated voltage waveforms of
2:1 ring-oscillator-based FD. (c) Simulated voltage waveforms of locked 4:1 ILFD. ..
................................................................................................................................ 22
Fig. 2-3. Chip micrograph for the ÷4 ILFD.............................................................. 23
Fig. 2-4. Measured operation frequency vs input power.. ......................................... 23
Fig. 2-5. Measured oscillation frequency, power consumption, locking range at 0 dBm
and FOM vs Vinj. ..................................................................................................... 24
Fig. 2-6. Measured spectra of the free-running and the locked ILFD........................ 25
Fig. 2-7. Measured operation frequency vs input power. .. ....................................... 25
Fig. 2-8. Measured spectra of the free-running and the locked ILFD ....................... 26
Fig. 2-9. Measured phase noises of the locked ILFD and the reference .................... 27
Fig. 2-10. Schematics of the implemented ÷4 ILFD and the improved ÷4 ILFD....... 28
Fig. 2-11. Simulated buffer voltage waveforms of original and improved circuit. ... 29
Fig. 2-12. Stand-alone ring-oscillator-based FD using NP cross-coupled pairs. . .... 30
Fig. 3-1. Block diagram of 8:1 quadrature ILFDs. Rfin: input signal. Rfo output signal.
(a) Voltage mode, (b) current-mode. (c) Voltage mode with three 2:1 FDs.. ............. 32
Fig. 3-2. (a) Block diagrams of quadrature VCO and 2:1 QFD. (b) Stand-alone ringoscillator-based FD. (c) Ring-oscillator-based FD using PMOS load.. ..................... 33
Fig. 3-3. Schematic of the voltage-mode ÷8 ILFD using shunt ILFDs...................... 34
Fig. 3-4. Simulated voltage waveforms: Injection voltage (purple), quadrature buffer
outputs .................................................................................................................. 37
Fig. 3-5. (a) Simulated free-run drain voltage waveforms of (M4, M5) and (M10, M11).
And simulated free-run voltage waveforms: (b) VDD= 0.8 V, (c) VDD= 1.4 V............. 37
Fig. 3-6. Chip micrograph for the ÷8 ILFD ............................................................. 38
Fig. 3-7. Measured operation frequency vs input power. . ........................................ 38
Fig. 3-8. Measured tuning range of the free-running ÷8 ILFD. . .............................. 38VIII
Fig. 3-9. Measured phase noises of the locked ÷8 ILFD and the reference.. ............. 39
Fig. 3-10. Equivalent circuit.... ................................................................................ 40
Fig. 3-11. Simulated voltage waveforms of ÷8 differential ILFD... .......................... 41
Fig. 3-12. Schematic of a divide-by-4 FD using two FDs in series.... ....................... 42
Fig. 3-13. (a) Schematic of a divide-by-4 FD. (b) Simulated voltage waveforms of ÷4
ring-oscillator FD... ................................................................................................. 43
Fig. 4-1. Schematic diagram of amplifiers... ............................................................ 45
Fig. 4-2. (a) Schematic diagram of class-AB oscillator. (b) Schematic diagram of
class-D oscillator... .................................................................................................. 46
Fig. 4-3. Schematic of the designed class-D VCO.................................................... 47
Fig. 4-4. (a) Simulated voltage and current waveforms of the designed VCO........... 47
Fig. 4-4. (b) Simulated oscillation frequency fosc of the VCO vs VDD = Vbias. ............ 47
Fig. 4-4. (c) Simulated oscillation frequency fosc of the designed VCO vs VDD. ........ 48
Fig. 4-4. (d) Simulated oscillation frequency fosc of the designed VCO vs Vbias......... 48
Fig. 4-5. Voltage and current waveforms of the class-D VCO and a reference VCO. 49
Fig. 4-6. Simulated phase noises of the designed class-D VCO................................ 49
Fig. 4-7. Chip micrograph for the VCO ................................................................... 50
Fig. 4-8. Measured VCO fosc, output power, power consumption vs Vbias.................. 50
Fig. 4-9. (a) Measured VCO frequency vs VDD. (b) Measured frequency vs Vbias...... 51
Fig. 4-10. Measured VCO output power vs Vout. ...................................................... 52
Fig. 4-11. (a) Schematic of the DC-DC converter. . ................................................. 52
Fig. 4-11. (b) Simulated voltage waveforms. VDD=0.8V, Vbias=0.2 V. Vbuffer=0.4 V.
Output voltage VDCO: red line. Oscillator-core output voltage VM1: green. AC-DC
rectifier output voltage VDCR: blue... . ...................................................................... 54
Fig. 4-11. (c) Simulated voltage waveforms. VDD=0.8V, Vbias=0.8 V. Vbuffer=0.4 V... . 54
Fig. 4-12. Chip micrograph for the DC-DC converter.. ............................................ 55IX
Fig. 4-13. Measured spectrum of the class-D VCO.. ................................................ 55
Fig. 4-14. Measured output dc voltage, current consumption, oscillation frequency,
oscillator output power versus input dc voltage. VDD=Vbias.. ..................................... 56

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