臺灣博碩士論文加值系統

低光源增強(LowLight Enhancement) 是一種針對低光環境下拍攝的影像處理 技術。當我們處於光線不足的場景中，攝影設備接收到的光源訊號有限，導致所拍攝出來的影像品質令人不滿意，在暗處難以辨識物體的細節及顏色。低光源增強的目的就是透過對影像進行特殊處理，提高其亮度、對比度和清晰度，從而提升在低光環境下的影像品質。
隨著硬體技術的發展，深度學習在低光源增強領域中廣泛應用並取得不錯的成績。然而，這類技術往往需要大量的運算成本，如高效的處理器、顯示卡和記憶體等。因此，將這種技術應用於即時攝影設備上往往不太實際。為此，本論文提出了一種低成本且有效的低光源增強方法以及相應的VLSI 電路設計。我們從現有的文獻中獲得啟發，以簡單的方式獲取增強因子並減少原本增強函式所需的迭代次數，從而設計了對應的VLSI 電路。
本論文所提出的VLSI 硬體架構使用Verilog HDL 設計，並使用Synopsys Design Compiler 與TSMC 40 nm 合成，其中工作頻率為200 MHz，總邏輯閘數量為7.321 k。

Lowlight enhancement is an image processing technique designed for improving the quality of images captured in lowlight environments. In such situations, the limited amount of light received by the camera results in unsatisfactory image quality, with difficulties in discerning object details and colors in dark areas. The objective of lowlight enhancement is to enhance the brightness, contrast, and sharpness of the image through specialized processing, thereby improving the image quality in lowlight conditions.
With the advancement of hardware technology, deep learning has been widely applied in the field of lowlight enhancement, achieving notable results. However, such techniques often require substantial computational resources, including efficient processors, GPUs, and memory. As a result, applying these techniques to realtime imaging devices is often impractical. To address this issue, this paper proposes a lowcost and efficient lowlight enhancement method, along with a corresponding VLSI circuit design. Inspired by existing literature, we have designed a VLSI circuit that simplifies the acquisition of enhancement factors and reduces the number of iterations required by the original
enhancement function.
The VLSI hardware architecture proposed in this paper is designed using Verilog HDL and synthesized using Synopsys Design Compiler with TSMC 40nm technology. It operates at a frequency of 200 MHz and has a total logic gate count of 7.321 k.

摘要 i
Abstract ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章緒論 1
1.1 研究背景 1
1.2 研究動機與方向 1
1.3 論文組織 3
第二章相關文獻探討 4
2.1 LIME 4
2.1.1 Retinex模型 4
2.1.2 LIME演算法流程 4
2.1.3 LIME增強結果 5
2.2 Retinex Net 5
2.2.1 Retinex Net網路框架 6
2.2.2 Retinex Net增強結果 6
2.3 EnlightenGAN 7
2.3.1 EnlightenGAN網路架構 7
2.3.2 EnlightenGAN增強結果 8
2.4 ZeroDCE++ 8
2.4.1 網路框架 8
2.4.2 網路架構 9
2.4.3 增強曲線 10
第三章本論文所提出的方法 12
3.1 完整演算法流程 12
3.2 Downsampling 13
3.3 所提出的增強因子估計 13
3.4 高斯模糊 14
3.5 Upsampling 15
3.6 增強函式反正規化 17
3.7 迭代結果 18
第四章VLSI硬體設計與實現 20
4.1 VLSI系統架構 20
4.2 Downsampling模組 21
4.3 Calculator模組 21
4.4 Gaussin Blur模組 22
4.5 Upsampling模組 22
4.6 Enhance模組 24
第五章實驗結果 25
5.1 主觀評估 25
5.2 客觀評估 28
5.2.1 NIQE 28
5.2.2 客觀評估數據 28
5.3 硬體數據驗證 29
5.4 硬體合成數據 30
第六章結論 31
6.1 結論 31
參考文獻 32

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