臺灣博碩士論文加值系統

　　本論文提出以脈衝擴增為基礎之全數位CMOS數位至時間轉換器(Digital-to-Time Converter, DTC)，其架構包含脈衝擴增電路(Pulse-Expanding Circuit, PEC)、脈衝檢查電路(Pulse-Checking Circuit, PCC)、可變增益時間放大器(Variable-Gain Time Amplifier, VGTA)以及時間扣抵電路(Time Subtractor, TS)，本DTC之核心電路為PEC，其包含之脈衝擴增單元為新提出之全數位緩衝器架構，相較於先前之反相器架構僅增加一顆反相器成本，經模擬驗證，其抵抗製程變異能力與解析度改善相較於反相器架構可分別提升約32%與50%；其後透過PCC偵測脈衝擴增寬度，再利用輸入數位值(S)透過VGTA獲得相應之脈衝擴增幅度，最後再藉由TS扣除原由PEC產生之脈衝寬度，是以其輸出時間只與S有關。本電路以TSMC 0.35-µm CMOS製程製作，電路面積為0.022 mm2，其模擬時間解析度為53微微秒(ps)，而積分非線性誤差(INL)則在-0.5~0.5 LSB之內。

關鍵字：全數位、CMOS、數位至時間轉換器、脈衝擴增。

An all-digital CMOS digital-to-time converter (DTC) based on pulse expansion is presented. The proposed DTC is composed of a cyclic pulse-expanding circuit (PEC), a pulse-checking circuit (PCC), a variable-gain time amplifier (VGTA), and a time subtractor (TS). The PEC is the core circuit based on a newly all-digital buffer-based scheme. Compared with a previous inverter-based one, the increased cost is a NOT gate only. The simulated improvements of 50% and 32% in the resolution and process variation were achieved, successfully validating the proposed technique. The PCC is used to check the pulse-expanding width. The digital input value from the VGTA selects the corresponding pulse-expanding amplitude. Finally, the TS is used to subtract the width generated by PEC. Therefore, the time generation can be related to the S. The proposed circuit was implemented in the TSMC 0.35-µm CMOS process and occupied a small area of 0.22 mm2. The simulated resolution is about 53 ps with an INL of -0.5 ~ 0.5 LSB.

Index term：All Digital, CMOS, Digital-to-Time Converter (DTC), Pulse Expansion.

目錄

摘要 I
ABSTRACT II
誌謝 II
目錄 IV
表目錄 VI
圖目錄 VII
一、 緒論 1
1.1 研究動機 1
1.2 論文架構 3
二、 數位至時間轉換器之文獻探討 4
2.1 數位至時間轉換器 4
2.1.1 絕對延遲時間架構 4
2.1.2 相對時間延遲架構 6
2.1.3 以延遲鎖定迴路實現之數位至時間轉換器 7
2.1.4 游標卡尺法之數位至時間轉換器 8
2.1.5 數位至時間轉換器之整理與比較 9
三、 以脈衝擴增為基礎CMOS數位至時間轉換器 10
3.1 研究目的 10
3.2 整體電路架構 11
3.3 脈衝擴增電路 (PEC) 13
3.3.1 循環圈之脈衝產生器 13
3.3.2 先前脈衝改變機制 15
3.3.3 脈衝擴增單元(PEU) 19
3.3.4 脈衝擴增延遲線 (PEDL) 19
3.4 脈衝檢查電路(PCC) 22
3.4.1 脈衝檢查電路運作功能(tcheck) 22
3.5 可變增益時間放大器(VGTA) 24
3.6 時間扣抵電路(TS) 25

3.7 脈衝中和技術 26
3.7.1 控制單元之脈衝中和 27
3.7.2 訊號分流處之脈衝中和 29
四、 電路設計與模擬 30
4.1 設計流程與規格考量 30
4.2 循環圈電路模擬 32
4.3 可變增益時間放大器、時間扣抵電路、總電路功能模擬 35
五、 量測結果、結論與未來展望 39
5.1 量測環境設定 39
5.2 量測步驟與結果 41
5.3 結論 45
5.4 問題與討論 46
參考文獻 47


表目錄

表2- 1數位至時間轉換器整理比較表 9
表5- 1量測儀器列表 39
表5- 2數位至時間模式之電路效能比較表 44
表5- 3本篇論文之規格總整理 45

圖目錄

圖1- 1 TMSP應用於類比與數位處理之示意圖 2
圖2- 1緩衝閘延遲為基礎之數位至時間轉換器架構圖與時序圖 4
圖2- 2暫存器為基礎之數位至時間轉換器架構圖與時序圖 5
圖2- 3二進制權重之數位置時間轉換器架構圖 6
圖2- 4以延遲鎖定迴路實現之數位至時間轉換器架構圖 7
圖2- 5以Vernier PLL實現之數位至時間轉換器之架構圖與時序圖 8

圖3- 1 以脈衝擴增為基礎之全數位CMOS數位至時間轉換器 11
圖3- 2脈衝擴增循環圈細部電路架構圖 11
圖3- 3整體電路工作時序圖 11
圖3- 4 脈衝擴增電路 13
圖3- 5控制單元之架構與時序圖 14
圖3- 6脈衝產生電路時序圖 15
圖3- 7全數位單端反閘式脈衝縮檢機制 15
圖3- 8全數位單端反閘式脈衝擴增機制 17
圖3- 9單端反閘式脈衝縮減與擴增解析度趨勢圖 18
圖3- 10全數位單端緩衝閘式脈衝擴增機制 19
圖3- 11脈衝擴增延遲線單元 20
圖3- 12 反閘架構與緩衝閘架構公式推導趨勢比較圖 21
圖3- 13 緩衝閘與反閘單端PEU之製程變異模擬趨勢圖 21
圖3- 14脈衝檢查電路圖 22
圖3- 15循環圈外接脈衝檢查電路圖 23
圖3- 16脈衝檢查電路時序圖 23
圖3- 17可變增益時間放大器電路圖 24
圖3- 18 VGTA電路數值判斷與選擇時序圖 24
圖3- 19時間扣抵電路圖 25
圖3- 20時間扣抵電路時序圖 25
圖3- 21循環圈中出現的變異點 26
圖3- 22循環圈脈衝中和示意圖 27
圖3- 23控制單元脈衝中和示意圖 28
圖3- 24訊號分流處之脈衝中和示意圖 29

圖4- 1晶片實作設計流程 31
圖4- 2緩衝閘式脈衝擴增電路架構圖 32
圖4- 3 PG模擬波形圖 32
圖4- 4 PEU溫度變異模擬結果 33
圖4- 5循環圈脈衝中和模擬功能驗證 34
圖4- 6 VGTA輸入數位值4之波形模擬結果 34
圖4- 7 VGTA輸入數位值8之波形模擬結果 35
圖4- 8 TS波形模擬結果 35
圖4- 9 DTC製程變異模擬結果 36
圖4- 10 DTC之積分非線性誤差 36
圖4- 11 DTC之微分非線性誤差 37

圖5- 1晶片量測過程示意圖 38
圖5- 2可程式恆溫恆濕箱 39
圖5- 3 LD1117應用電路圖與實作圖 39
圖5- 4 IC顯微照 41
圖5- 5 核心電路顯微照 41
圖5- 6脈衝擴增循環圈量測結果 42

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