|
[1]H. P. Graf et al., "A massively parallel digital learning processor," in Advances in Neural Information Processing Systems, 2009, pp. 529-536. [2]Z. Li et al., "Laius: an 8-bit fixed-point CNN hardware inference engine," in 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017, pp. 143-150: IEEE. [3]L. Gong, C. Wang, X. Li, H. Chen, X. J. I. T. o. C.-A. D. o. I. C. Zhou, and Systems, "Maloc: A fully pipelined fpga accelerator for convolutional neural networks with all layers mapped on chip," vol. 37, no. 11, pp. 2601-2612, 2018. [4]H. Elloumi, D. Sellami, H. Rabah, M. J. A. J. f. S. Krid, and Engineering, "A Highly Flexible Architecture for Morphological Gradient Processing Implemented on FPGA," vol. 45, no. 4, pp. 2675-2684, 2020. [5]H. Samet, M. J. I. t. o. p. a. Tamminen, and m. intelligence, "Efficient component labeling of images of arbitrary dimension represented by linear bintrees," vol. 10, no. 4, pp. 579-586, 1988. [6]Y. Qi and G. J. I. C. V. Zhang, "Strategy of active learning support vector machine for image retrieval," vol. 10, no. 1, pp. 87-94, 2016. 柒、
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