目錄

摘要 I
ABSTRACT II
誌謝 III
目錄 IV
表目錄 VI
圖目錄 VII
一、 緒論 1
1.1 研究動機 1
1.2 論文架構 3
二、 類比至數位轉換器與溫度至數位轉換器 之文獻探討 4
2.1 類比至數位轉換器 4
2.1.1 益步調製之類比至數位轉換器 4
2.1.2 流水線之類比至數位轉換器 5
2.1.3 基於時間縮放類比至數位轉換器 6
2.1.4 循環式類比至數位轉換器 7
2.1.5 積分式類比至數位轉換器 8
2.1.6 類比至數位轉換器整理比較 9
2.2 溫度感測器 10
2.2.1 熱敏電阻式感測器 11
2.2.2 積體電路式感測器 11
2.2.3 電阻式溫度感測器 11
2.2.4 熱電耦式溫渡感測器 12
2.3 積體電路感測器 13
2.3.1 積體電路式之電壓感測器 13
2.3.2 積體電路式之時域感測器 18
三、 具溫度感測功能CMOS之時域類比轉換器 21
3.1 研究目的 21
3.2 整體電路架構 22
3.3 可變壓控延遲時間循環電路(VCDL) 24
3.3.1 內建於循環圈之脈衝產生器 24
3.3.2 全數位單級INV並聯機制 27
3.3.3 全數位雙級混合並聯機制 29
3.3.4 全數為四級混合並聯機制 33
3.3.5 壓控延遲線(VDL) 35
3.3.6 脈衝寬度選擇變化單元(PWSU) 36
3.4 為解決偏移誤差問題之時間增加偵測電路 37
3.4.1 脈衝寬度偵測電路(PWDC) 38
3.5 可變增益時間放大(VGTA) 40
3.6 脈衝中和技術 42
3.6.1 控制單元之脈衝中和 44
3.6.2 解多工之脈衝中和 45
3.6.3 多工器之脈衝中和 46
四、 電路設計與模擬 47
4.1 設計流程與規格考量 47
4.2 脈衝寬度變化單元模擬 50
4.3 溫度感測器模擬 51
4.4 類比至數位感測器模擬 51
4.5 脈衝中和技術模擬 53
五、 量測結果、結論與未來展望 48
5.1 實際量測與環境設定 54
5.2 量測順序與結果 57
5.3 結論 64
5.4 問題討論與未來展望 65
參考文獻 66

[1]Frank M. Wanlass, “Low stand-by power complementary field effect circuitry,” U.S. Patent 3356858, Dec. 5, 1967
[2]Atiyeh Karimlou; Mohammad Yavari, “A Time-Based Analogue-to-Digital Converter for ECG Applications,” 29th Iranian Conference on Electrical Engineering (ICEE), 2021
[3]Sunkyu Kong; Bumhee Bae; Dong-Hyun Kim; Hongseok Kim; Chiuk Song; Joungho Kim, “Electromagnetic interference on analog-to-digital converters from high-power wireless power transfer system for automotive charger,” IEEE International Symposium on Electromagnetic Compatibility (EMC), 2016
[4]Narmin Samimian; Morteza Mousazadeh; Abdollah Khoie, “A Time-based All-Digital Analog to Digital converter for IOT Applications,” 27th Iranian Conference on Electrical Engineering (ICEE), 2019
[5]Kazuki Kuribayashi; Kazuya Machida; Yuji Toyama; Takao Waho, “Time-Domain Multi-bit Delta\Sigma Analog-to-Digital Converter,” 41st IEEE International Symposium on Multiple-Valued Logic), 2011
[6]Hwi-Cheol Kim; Deog-Kyoon Jeong; W. Kim, “A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters,” IEEE Transactions on Circuits and Systems I: Regular Papers), vol. 53, Issue. 4, 2006
[7]Huang Xiaozong; Zhang Jing; Gao Weiqi; Shi Jiangang; Wan Hui, “A 16-bit, 250ksps successive approximation register ADC based on the charge-redistribution technique,” IEEE International Conference of Electron Devices and Solid-State Circuits, 2011
[8]Serhii M. Zakharchenko; Tetiana I. Troianovska, “Method of cyclic ADC calibration by the conversion characteristics analysis,” 2nd International Conference on Advanced Information and Communication Technologies (AICT), 2017
[9]Ehsan Rahiminejad; Reza Lotfi, “A low-power architecture for integrating analog-to-digital converters,” 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)), 2009
[10][Agilent Technologies., “Practical Temperature Measurements,” Jan. 2012.
[11]A. BAKKER, “CMOS Smart Temperature Sensors – An Overview,” Proc. IEEE Sensors, vol. 2, pp. 1423-1427, Jun. 2002.
[12]K. E. Kuijk, “A precision reference voltage source,” IEEE Journal of Solid-State Circuits, vol. 8, no. 3, pp. 222-226, Jun. 1973.
[13]A. Bakker and J. H. Huijsing, “Micropower CMOS temperature sensor with digital output,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 933–937, Jul. 1996.
[14]M.-C. Weng and J.-C. Wu, “A Temperature sensor in 0.6μm CMOS Technology,” IEEE Asia Pacific CNF, pp. 116-119, Aug. 1999.
[15]K. Souri, et al., “A 0.85V 600nW All-CMOS Temperature Sensor with an Inaccuracy of ±0.4°C (3σ) from -40 to 125°C,” IEEE International Solid-State Circuits Conference, Feb. 2014.
[16]Heidary, et al., “A BJT-Based CMOS Temperature Sensor with a 3.6pJ·K2-Resolution FoM,” IEEE International Solid-State Circuits Conference, Feb. 2014.
[17]G. Wang, and G.C.M. Meijer, “The Temperature Characteristics of Bipolar Transistors Fabricated in CMOS Technology,” Sens. Actuat., vol. 87, pp. 81-89, 2000.
[18]P. Chen, C.-C. Chen, W.-F. Lu and C.-C. Tsai, “A Time-to-Digital-Converter-Based CMOS Smart Temperature Sensor,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1642-1648, Aug. 2005.
[19]Nguyen Thanh Trung , Kwansu Shon, and Soo-Won Kim “A Delay Line with Highly Linear Thermal Sensitivity for Smart Temperature Sensor,” in Proc. 50th MWSCAS, pp. 899-902, Aug. 2007.
[20]P. Chen, M.-C. Shie, Z.-Y. Zheng, Z.-F. Zheng and C.-Y. Chu, “A Fully Digital Time Domain Smart Temperature Sensor Realized with 140 FPGA Logic Elements”, IEEE Transactions on Circuits And Systems I, vol. 54, pp. 2661-2668, Dec. 2007.
[21]M. K. Law and A. Bermak, “A Time Domain Differential CMOS Temperature Sensor with Reduced Supply Sensitivity,” IEEE International Symposium on Circuits and Systems, pp. 2126-2129, May. 2008.
[22]C.-C. Chen et al., “All-Digital Pulse-Shrinking Time-to-Digital Converter with Improved Dynamic Range,” American Institute of Physics, Review of Scientific Instruments, vol. 87, no. 4, pp. 046104(1-3), Apr. 2016.
[23]R. B. Stazewski, D. Leipold, C.-M. Hung, and P. T. Balsara, “TDC-Based Frequency Synthesizer for Wireless Applications,” IEEE RFIC Symposium, pp. 215-218, June 2004.
[24]張凱翔，2019，具內建偏移誤差消除之CMOS脈衝縮減式時間至數位轉換器，國立高雄科技大學，碩士論文。
[25]Chun-Chi Chen, Chorng-Sii Hwang, and Che-Shun Chu, C.-M. Hung, and P. T. Balsara, Area-efficient all-digital pulse-shrinking smart temperature sensor with improved accuracy and resolution,” : Review of Scientific Instruments 89, June 2018.
[26]Poki Chen; Chun-Chi Chen; Yu-Han Peng; Kai-Ming Wang; Yu-Shin Wang, A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of −0.4°C ∼ +0.6°C Over a 0°C to 90°C Range,” : Volume: 45, Issue: 3,, March 2010.
[27]Poki Chen; Tuo-Kuang Chen; Yu-Shin Wang; Chun-Chi Chen, A Time-Domain Sub-Micro Watt Temperature Sensor With Digital Set-Point Programming,” : IEEE Sensors Journal, Vol: 9, Issue: 12, December 2009
[28]Hua Fan; Tongrui Xu; Jianming Liu; Quanyuan Feng, Design of an All-digital Time Domain Analog-to-digital Converter Based on Ring Delay Line Technology,” International Conference on IC Design and Technology (ICICDT),2021
[29]C.-C. Chen, et. al., “All-Digital Pulse-Shrinking Time-to-Digital Converter with Improved Dynamic Range,” Review of Scientific Instruments, vol. 87, no. 4, pp. 046104(1-3), Apr. 2016.
[30]朱哲勳，2017，基於脈衝擴增之全數位CMOS數位至時間轉換器，國立高雄第一科技大學，碩士論文。
[31]R. Szplet et al., “An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking,” IEEE Trans. Instrum. Meas., vol. 59, no. 6, pp. 1663-1670, June. 2010.
[32]C.-C. Chen, et al., “C All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters,” Rev. Sci. Instrum., vol. 86, no. 12, Dec. 2015.
[33]National Semiconductor, “LM117/LM317A/LM317 3-Terminal Adjustable Regulator General Description”, Oct. 2008.
[34]C.-C. Chen, et al., “CMOS time-to-digital converter based on a pulse-mixing scheme,” Rev. Sci. Instrum., vol. 85, no. 11, pp. 114702(1–9), Nov. 2014.
[35]朱哲勳，2017，基於脈衝擴增之全數位CMOS數位至時間轉換器，國立高雄第一科技大學，碩士論文。
[36]C. K. Kim, B. S. Kong, C. G. Lee and Y. H. Jun, “CMOS Temperature Sensor with Ring Oscillator for Mobile DRAM Self-refresh Control,” IEEE International Symposium on Circuits and Systems, pp. 3094-3097, May. 2008.
[37]T. Anand, A. A. Makinwa and P. K. Hanumolu, “A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity,” IEEE Journal of Solid-State Circuits, vol. 51, no. 11, pp. 2651-2663, Nov. 2016.
[38]R. Quan, U. Sonmez, F. Sebastiano, and K. A. A. Makinwa, “A 4600 μm2 1.5 °C (3σ) 0.9 kS/s thermal-diffusivity temperature sensor with VCO-based readout,” in IEEE ISSCC Dig. Tech. Papers, pp. 1–3, Feb. 2015.
[39]S. Hwang, J. Koo, K. Kim, H. Lee, and C. Kim, “A 0.008 mm2 500 μW 469 kS/s frequency-to-digital converter based CMOS temperature sensor with process variation compensation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 9, pp. 2241–2248, Sep. 2013.
[40]Chun-Chi Chen; Chao-Lieh Chen; Wei Fang; Yen-Chan Chu, “All-Digital CMOS Time-to-Digital Converter With Temperature-Measuring Capability,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, Issue: 9, 2020.
[41]Z. Xu, S. Lee, M. Miyahara, and A. Matsuzawa, “A 0.84 ps-LSB 2.47 mW time-to-digital converter using charge pump and SAR ADC,” in Proc. IEEE CICC, 2013, pp. 1–4.
[42]Y. Kim and T. K. Kim, “An 11 b 7 ps resolution two-step time-to-digital converter with 3-D Vernier space,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 8, pp. 2326–2336, Aug. 2014.
[43]Y. H. Seo, J. S. Kim, H. J. Park, and J. Y. Sim, “A 1.25 ps resolution 8b cyclic TDC in 0.13 um CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 736–743, Mar. 2012.
[44]M. Lee and A. A. Abidi, “A 9b, 1.25 ps resolution coarse-fine time-todigital converter in 90 nm CMOS that amplifies a time residue,” in Proc. IEEE Symp. VLSI Circuits, 2007, pp. 168–169.
[45]Jiangbo Wei, Chenghao Zhang, Maliang Liu, “A 11-Bit 1-GS/s 14.9mW Hybrid Voltage-Time Pipelined ADC With Gain Error Calibration,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol: 69, Issue: 3, 2022