臺灣博碩士論文加值系統

近年來通信產業需求量增加，第五代通訊系統的需求也在增加，通訊的好壞與接收及發送端有著重要的關係，在接收端中壓控振盪器、低雜訊放大器以及混頻器扮演著非常重要的地位，因此本文在此研究之具有低功耗雙頻帶CMOS壓控振盪器使用TSMC 0.18 µm CMOS製程來實現，實現提供1.2V電壓時低頻3.397 ~ 3.678GHz高頻7.206 ~ 7.572GHz低頻與高頻相位雜訊分別為-118.18 dBc/Hz ~ -114.82 dBc/Hz和，而調諧範圍分別為7.9%以及5%，消耗功率在1.2V=4.2mW，KVCO為150GHz/V。
本文在第二章的具有5G應用的雙頻帶壓控振盪器量測結果在1.7V下低頻段為0.991 ~ 1.221GHz高頻段為2.845 ~ 3.215GHz相位雜訊在低頻為-100.33 dBc/Hz高頻為-107.41 dBc/Hz調諧範圍在低頻時為14%高頻為5.4%電流為6.2mA而KVCO為60 GHz/V。
在第三章提出的應用於5G具有高效能低雜訊放大器在事後模擬中，供應1.8V時S11為-13.095 dB S22為-17.693 dB S21為7.278 dB P1dB為-16.953 dBm 相位雜訊為6.173 dB IIP3為7 dBm而穩定度都大於1。
在第四章所提出的設計應用於5G降頻器事後模擬中顯示在供應電壓為1.8V時S11、S33分別為-11.423 dB以及-16.982 dB轉換增益為1.332 dB相位雜訊為51.411 dB最後P1dB以及IIP3分別顯示為-9.427 dBm和1 dBm。

In recent years, wireless communication demands for the fifth-generation communication systems have been increased. This thesis presents a receiver including two voltage-controlled oscillators (VCOs), a low-noise amplifier (LNA), and a downconversion mixer.
In Chapter 2, the two proposed VCOs are implemented in the UMC 0.18-μm and TSMC 0.18-μm process technologies, respectively. The first proposed VCO presents a dual-band function. The measured tuning ranges are from 0.991 to 1.221 GHz for the low frequency band corresponding to 14 % tuning range and from 2.845 to 3.215 GHz for the high frequency band corresponding to 5.4 % tuning range, respectively. The measured phase noise for the low and high bands is -100.33 dBc/Hz at 1-MHz offset and -107.41 dBc/Hz at 1-MHz offset, respectively. The core current is 6.2mA from a supply voltage of 1.7 V. The second proposed VCO also presents a dual-band function. The measured tuning ranges are from 3.397 to 3.678 GHz for the low frequency band corresponding to 7.9 % tuning range and from 7.206 to 7.572 GHz for the high frequency band corresponding to 5 % tuning range, respectively. The measured phase noise for the low and high bands is -118.18 dBc/Hz at 1-MHz offset and -114.82 dBc/Hz at 1-MHz offset, respectively. The core power consumption is 4.2 mW from a supply voltage of 1.2 V.
In Chapter 3, the proposed high-efficiency LNA is designed in the TSMC 0.18-μm process technology. The simulated S11, S22, and S21 are -13.095 dB, -17.693 dB, and 7.278 dB, respectively. The simulated P1dB and IIP3 are -16.953 dBm and 7 dBm, respectively. The simulated power consumption is 3.55 mW from a supply voltage of 1.8 V
In Chapter 4, the proposed down-conversion mixer is designed in the TSMC 0.18- μm process technology. The simulated S11 and S33 are -11.423 dB and -16.982 dB, respectively. The simulated conversion gain is 1.332 dB. Besides, the simulated P1dB and IIP3 are -9.427 dBm and 1 dBm, respectively. The simulated power consumption is 2.197 mW from a supply voltage of 1.8 V.

摘要............................................................i
Abstract......................................................ii
誌謝...........................................................iv
目錄...........................................................v
表目錄......................................................vii
圖目錄......................................................viii
第一章 緒論................................................1
1.1 研究背景...............................................1
1.2 設計流程...............................................1
1.3 研究方向...............................................2
1.4 論文架構...............................................2
第二章 壓控振盪器......................................3
2.1 壓控振盪器介紹.....................................3
2.2 壓控振盪器架構與參數..........................3
2.2.1 相位雜訊.............................................4
2.2.2 調諧範圍.............................................4
2.3 具有5G應用的雙頻帶壓控振盪器...........5
2.3.1 設計電路.............................................5
2.3.2 實驗結果...........................................10
2.3.3 討論..................................................15
2.4 具有低功耗雙頻帶CMOS壓控振盪器...16
2.4.1 設計電路...........................................16
2.4.2 實驗結果...........................................20
2.4.3 討論..................................................25
第三章 低雜訊放大器.................................26
3.1 低雜訊放大器介紹...............................26
3.2 低雜訊放大器架構與參數....................26
3.2.1 S參數...............................................26
3.2.2 雜訊指數..........................................27
3.2.3 1dB增益壓縮點................................27
3.2.4 三階截斷點......................................28
3.3 應用於5G具有高效能低雜訊放大器....29
3.3.1 設計電路..........................................29
3.3.2 實驗結果..........................................32
3.3.3 討論.................................................35
第四章 混頻器...........................................36
4.1 混頻器介紹..........................................36
4.2 混頻器架構與參數..............................36
4.2.1 S參數..............................................38
4.2.2 轉換增益.........................................38
4.2.3 雜訊指數.........................................38
4.2.4 1dB增益壓縮點...............................38
4.3 應用於5G降頻器設計.........................39
4.3.1 設計電路..........................................39
4.3.2 實驗結果..........................................42
4.3.3 討論.................................................45
第五章 結論...............................................46
參考文獻...................................................47
Extended Abstract....................................49

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