本論文提出CMOS時間至數位與數位至時間雙功能資料轉換器，可以單一轉換器實現數位至時間器(Digital-to-Time Converter, DTC)與時間至數位器(Time-to-Digital Converter, TDC)功能，如此可增加元件使用效率來節省成本以及電路附加價值。本研發電路包含脈衝變化電路、時間增加偵測電路以及數值判斷與脈衝擷取電路，其中脈衝寬度變化電路內建控制單元與時間增加延遲線來產生時間增加脈衝(tA)，再利用所提出之脈衝改變(擴增與縮減)機制來精簡地分別實現DTC模式及TDC模式；而精簡之時間增加偵測電路則用於偵測tA以解決偏移誤差問題；最後，利用計數器計數脈衝縮減次數以輸出數位值，達成TDC功能；或是由數值判斷與擷取電路輸出相應於數位輸入碼之時間寬度，達成DTC功能。本論文以TSMC 0.18-μm CMOS製程實作，其面積為 0.138 mm2，其中DTC之量測解析度為19 ps/LSB，積分非線性誤差接近±1 LSB；TDC方面，其有效解析度約為14 ps/LSB，積分非線性誤差則在±0.2 LSB之間。

A CMOS dual-function data converter for time-to-digital and digital-to-time conversion (TDC&DTC) is presented. Innovatively, only a single converter performs the two conversions, which effectively increases the usage efficiency of components for cost-saving and added value. The proposed converter consists of a pulse-varying circuit (PVC), a time-added detected circuit (TADC), and a pulse-capturing circuit. The PVC contains two simple control units and a time-added delay line to generate a time-added pulse (tA) firstly. Then, the proposed pulse-varying (expanding/shrinking) mechanism is used to perform DTC and TDC functions. The TADC with lower complexity is used to detect the tA for the cancellation of offset error. Finally, the counter is used for digital output in the TDC mode. In DTC mode, the counter is modified as the pulse-capturing circuit for outputting the time generation corresponding to the numeric input value. The proposed circuit is fabricated with TSMC 0.18-μm CMOS process and has a small area of approximately 0.138 mm2. For DTC mode, the measured resolution reaches about 19 ps, with an integral nonlinearity of approximately ±1 LSB. For TDC mode, the achieved resolution is nearly 14 ps with an INL of ± 0.2 LSB.

摘要 I
ABSTRACT II
誌謝 III
目錄 IV
表目錄 VI
圖目錄 VII
一、 緒論 1
1.1 研究動機 1
1.2 論文架構 3
二、 數位至時間轉換器與時間至數位轉換器 之文獻探討 4
2.1 數位至時間轉換器 4
2.1.1 絕對延遲時間架構之數位至時間轉換器 4
2.1.2 以電容內插法實現之數位至時間轉換器 6
2.1.3 以延遲鎖定迴路實現之數位至時間轉換器 7
2.1.4 游標卡尺法之數位至時間轉換器 8
2.1.5 數位至時間轉換器之整理與比較 9
2.2 時間至數位轉換器 10
2.2.1 脈衝縮減法之時間至數位轉換器 10
2.2.2 計數器法之時間至數位轉換器 11
2.2.3 游標卡尺法之時間至數位轉換器 12
2.2.4 時間轉換器整理比較 13
三、 CMOS時間至數位與數位至時間 雙功能資料轉換器 14
3.1 研究目的 14
3.2 整體電路架構 15
3.3 二進制權重脈衝寬度變化電路 (BWPVC) 17
3.3.1 內建於循環圈之脈衝產生器 17
3.3.2 全數位MOS電容機制 19
3.3.3 二進制權重脈衝擴增單元(BWPEU) 23
3.3.4 脈衝寬度變化單元 (PVU) 24
3.4 為解決偏移誤差問題所提出之新穎的時間增加偵測電路 26
3.4.1 修正之時間增加偵測電路(TADC) 27
3.5 數值判斷與擷取電路(VCPCC) 32
3.6 脈衝中和技術 34
3.6.1 控制單元之脈衝中和 36
3.6.2 訊號分流處之脈衝中和 37
3.6.1 多工器之脈衝中和 38
四、 電路設計與模擬 40
4.1 設計流程與規格考量 40
4.2 脈衝寬度變化單元模擬 43
4.3 時間/數位雙功能資料轉換器模擬 46
五、 量測結果、結論與未來展望 48
5.1 量測環境設定 48
5.2 量測步驟與結果 51
5.3 結論 57
5.4 問題與討論 58
參考文獻 59

[1]Frank M. Wanlass, “Low stand-by power complementary field effect circuitry,” U.S. Patent 3356858, Dec. 5, 1967
[2]C. S. Taillefer, et al., “Delta–Sigma A/D conversion via time-mode signal processing” IEEE Trans. Circuits Syst. I, vol. 56, no. 9, pp. 1908–1920, Sep. 2009.
[3]Gordon W., et al., “A Brief Introduction to Time-to-Digital and Digital-to-Time Converters,” IEEE Trans. Circuits Syst. II, vol. 57, no. 3, pp. 153–157, Mar. 2010.
[4]P. Chen, et al., “FPGA Vernier Digital-to-Time Converter With 1.58 ps Resolution and 59.3 Minutes Operation Range,” IEEE Trans. Circuits Syst., vol. 57, no. 6, pp. 1134–1142, June 2010.
[5]T. Okayasu, et al., “1.83 ps-Resolution CMOS dynamic arbitrary timing generator for ATE applications” IEEE ISSCC, pp. 2122-2131, Feb. 2006.
[6]J. A. Gasbarro, et al., “Integrated Pin Electronics for VLSI Functional Testers” IEEE J. Solid-State Circuits, vol.24, no.2, pp. 331-337, Apr. 1989.
[7]C.-W. Branson, et al., “Integrated pin electronics for a VLSI test system,” IEEE Transaction on Industrial Electronics, vol. 36, no. 2, pp. 185–191, May 1989.
[8]J. Christiansen, “An integrated high resolution CMOS timing generator based on an array of delay locked loops,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 952–957, July 1996.
[9]E. Räisänen-Ruotsalainen, et al., “An integrated time-to-digital converter with 30-ps single-shot precision,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1507-1510, Oct. 2000.
[10]A. H. Chan and G. W. Roberts, “A jitter characterization system using a component-invariant vernier delay line,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 1, pp. 79-95, Jan. 2004.
[11]T. Xia, et al., “Self-refereed on-chip jitter measurement circuit using vernier oscillators,” IEEE Computer Society Annual Symp. VLSI, pp. 218-223, May 2005.
[12]R. Nutt, “Digital time intervalometer,” Rev. Sci. Instrum, vol. 39, no. 9, pp. 1342-1345, 1968.
[13]E.-R Ruotsalainen, T. Rahkonen and J. Kostamovaara, “A low-power CMOS time-to-digital converter,” IEEE Journal of Solid-State Circuits, vol. 30, Issue 9, pp. 984-990, Sep. 1995.
[14]Agilent Technologies., “Practical Temperature Measurements,” Jan. 2012.
[15]張凱翔，2019，具內建偏移誤差消除之CMOS脈衝縮減式時間至數位轉換器，國立高雄科技大學，碩士論文。
[16]C.-C. Chen, et al., “C All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters,” Rev. Sci. Instrum., vol. 86, no. 12, Dec. 2015.
[17]C.-C. Chen, et al., “All-Digital Cost-Efficient CMOS Digital-to-Time Converter Using Binary-Weighted Pulse Expansion,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 4, pp. 1094-1098, April 2020.
[18]陳彥呈，2018，具精簡製程變異校正之全數位CMOS脈衝縮減時間至數位轉換器，國立高雄科技大學，碩士論文。
[19]C.-C. Chen, et. al., “All-Digital Pulse-Shrinking Time-to-Digital Converter with Improved Dynamic Range,” Review of Scientific Instruments, vol. 87, no. 4, pp. 046104(1-3), Apr. 2016.
[20]R. Szplet, et al., “An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking,” IEEE Trans. Instrum. Meas., vol. 59, no. 6, pp. 1663-1670, June. 2010.
[21]朱哲勳，2017，基於脈衝擴增之全數位CMOS數位至時間轉換器，國立高雄科技大學，碩士論文。
[22]Behzad Razavi, “Principles of Data Conversion System Design,” IEEE Press, 1995.
[23]Van De Plassche, et al., “Integrated Analog-to-Digital and Digital-to-Analog Converters,” Kluwer Academic Publishers, 1994.
[24]C.-C. Liu, et al., “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, 2010.
[25]Texas Instrments, “TXB0104 4-Bit Bidirectional Voltage-level Translator With Automatic Direction Sensing and ±15-kV ESD Protection,” Mar. 2018.
[26]STMicroelectronics, “LD1117 Adjustable and fixed low drop positive voltage regulator,” Feb. 2020.
[27]B. Arkin, “Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers,” IEEE ISSCC, 2004, pp. 348–349.
[28]J. A. Gasbarro, et al., “Integrated Pin Electronics for VLSI Functional Testers,” proc. IEEE CICC, 1989, pp. 331–337.
[29]N. Pavlovic, et al., “A 5.3 GHz digital-to-time-converter based fractional-N all-digital PLL,” IEEE ISSCC, 2011, pp. 54–56.
[30]C.-C. Chen, et al., “All-digital CMOS MOS-capacitor-based pulse-shrinking-mechanism,” Review of Scientific Instruments, vol. 86, no. 12, pp. 126113(1-3), 2015
[31]Y.-H. Kao et al., “A Direct-Sampling Pulsed Time-of-Flight Radar With Frequency-Defined Vernier Digital-to-Time Converter in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2665–2677, Nov. 2015.
[32]Yue Liu, et al., “Multi-stage Pulse Shrinking Time-to-Digital Converter for Time Interval Measurements,” European Microwave Integrated Circuit Conference, pp. 267-270, Oct., 2007.
[33]C.-C. Chen, et al., "A Low-Cost CMOS Smart Temperature Sensor Using a Thermal-Sensing and Pulse-Shrinking Delay Line," IEEE Sensors Journal, vol. 14, no. 1, pp. 278-284, Jan. 2014.
[34]P. Chen, et al., “A CMOS pulse-shrinking delay element for time interval measurement,” IEEE Trans. Circuits Syst. II, vol. 47 no. 9, pp. 954–958, Sep. 2000.
[35]R. Enomoto et al., “A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18- μ m CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1,pp. 11-19, Jan. 2019.