本論文提出兩種低輸出電壓變化低功率消耗BiCMOS參考電壓電路。第一種電路是利用BJT模組產生正溫度係數與MOSFET偏壓於弱反轉區的臨界電壓所產生負溫度係數，適當組合正溫度係數和負溫度係數以達成零溫度係數參考電壓。本電路在電源端串聯一顆電阻，降低電源電壓變動對輸出參考電壓的影響。給與±0.1V的電源電壓變化，觀察電源電壓變動對輸出參考電壓的影響。第二種則是將電路中所有的MOSFET都偏壓在弱反轉區。並且加入一個串聯電阻以吸收電源電壓的變化量。這兩種電路皆具有MOS電晶體偏壓在弱反轉區時具有低功耗的特性。

本論文中的各種參考電壓電路除了提供詳細的設計原理之外，還使用了HSPICE與ADE(Analog Design Environment)這兩種電路模擬軟體執行佈局前/後模擬，佈局前與佈局後模擬結果皆與設計理論相符合，也證明電路的可行性。也利用TSMC 0.35微米與TSMC 0.18微米製程參數進行晶片實作。供應電壓分別是2V與1.8V，佈局後模擬顯示溫度變化範圍則是-30°C遞增至130°C，輸出變化量最小可達14.3 ppm/°C與2.94 ppm/°C。

In this thesis, we have proposed two BiCMOS reference voltage circuit of low power and low output variation. The first proposed circuit uses the positive temperature coefficient voltage obtained from the BJT module and the negative temperature coefficient voltage from the threshold voltage of a weak-inversion biased MOSFET. Proper combination of the positive and negative temperature-coefficient voltages, a zero temperature-coefficient reference voltage can be given. In the proposed circuit, a series resistor is connected to the supply voltage to reduce the output voltage variation caused by the fluctuations of the supply voltage. When there is ±0.1V change in the supply voltage, observing the corresponding output voltage variation from the fluctuations. The second proposed circuit kept all MOSFET in the weak inversion region and added a series resistor to absorb the output voltage variation. In all the proposed circuits, MOS transistors are biased in the weak inversion region to achieve the low-power consumption characteristics.

Detailed design principles have been disclosed in this thesis, The HSPICE and ADE (Analog Design Environment) simulation programs have been used to perform the pre-layout and post-layout simulations. Both the pre-layout and post-layout simulation results are consistent with the design theory, and also prove the validity of the proposed circuits. The proposed circuits have been implemented by using the 0.35μm and 0.18μm process parameters. The supply voltages of the proposed circuit are 2V and 1.8V, respectively. The post-layout simulation was performed, the temperature ranges from -30°C to 130°C, and the minimum output variation can be 14.3 ppm/°C and 2.94 ppm/°C, respectively.

摘要......i
Abstract......ii
誌謝......
目錄......
表目錄......
圖目錄......
符號說明......
第一章 緒論......
1.1 積體電路發展沿革......1
1.2 設計流程......1
1.3 研究方向與重點......2
1.4 論文架構簡介......2
第二章 參考電壓介紹......3
2.1 參考電壓簡介......3
2.2 參考電壓電路工作原理......3
2.3 BJT 參考電壓電路......5
‧2.3.1 負溫度係數特性......5
‧2.3.2 正溫度係數特性......6
‧2.3.3 BJT 參考電壓電路......7
2.4 MOSFET 參考電壓電路架構......8
‧2.4.1 弱反轉區與溫度特性......8
‧2.4.2 MOSFET 參考電壓電路......10
第三章 低輸出電壓變化低功率消耗 BiCMOS 參考電壓設計......13
‧3.1 BiCMOS 參考電壓電路......13
‧3.2 TSMC 0.18μm 製程佈局前模擬......14
‧3.2.1 第一種改良型 BiCMOS 參考電壓電路......16
‧3.2.2 第一種改良型 BiCMOS 參考電壓電路分析......16
‧3.3 電路模擬結果......18
‧3.3.1 TSMC 0.18μm 製程佈局前模擬......18
‧3.3.2 TSMC 0.18μm 製程佈局後模擬......20
‧3.3.3 TSMC 0.35μm 製程佈局前模擬......22
‧3.3.4 TSMC 0.35μm 製程佈局後模擬......23
‧3.4 第一種改良型 BiCMOS 電路(Q1 與 Q2 使用 NPN 型電晶體)......25
‧3.4.1 TSMC 0.18μm 製程佈局前模擬......26
‧3.4.2 TSMC 0.18μm 製程佈局後模擬......27
‧3.5 TSMC 0.18μm 與 TSMC 0.35μm 製程後模擬效能比較表......29
第四章 低功率參考電壓設計......31
‧4.1 低功率 BiCMOS 參考電壓電路......31
‧4.2 第二種改良型 BiCMOS 參考電壓電路分析......32
‧4.3 電路模擬結果......33
‧4.3.1 TSMC 0.35μm 製程佈局前模擬......33
‧4.3.2 TSMC 0.35μm 製程佈局後模擬......35
‧4.3.3 TSMC 0.18μm 製程佈局前模擬......37
‧4.3.4 TSMC 0.18μm 製程佈局後模擬......35
‧4.4 第二種改良型 BiCMOS 參考電壓電路......40
‧4.4.1 TSMC 0.18μm 製程佈局前模擬......41
‧4.4.2 TSMC 0.18μm 製程佈局後模擬......42
‧4.5 TSMC 0.18μm 與 TSMC 0.35μm 製程後模擬效能比較表......44
第五章 晶片實作與量測結果......46
‧5.1 全客製化 IC......46
‧5.2 量測儀器與流程......48
‧5.3 第一種改良型 BiCMOS 參考電壓電路晶片實體與量測結果......49
‧5.3.1 晶片實體......49
‧5.3.2 晶片量測......50
‧5.4 第二種改良型 BiCMOS 參考電壓電路晶片實體與量測結果......52
‧5.4.1 晶片實體......52
‧5.4.2 晶片量測......53
第六章 結論與討論......56
參考文獻......57

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