本論文研究18~24GHz頻段的低雜訊放大器(Low Noise Amplifier, LNA)電路為主，在射頻收發機中低雜訊放大器扮演重要角色，在接收到信號的同時要有良好的雜訊、增益和穩定度作為輸出。本電路是使用串接電路設計，電路之第一級主要以低雜訊與良好輸入匹配為主，第二級與第三級則是透過串接與回授來提高電路增益與穩定度，進而設計出有良好的增益以及穩定度與較低的雜訊。而本研究所採用的0.15μm pHEMT製程是由穩懋半導體公司(WIN Semiconductors Corp)所提供，並對此電路架構模擬結果進行分析比較。

第一部分設計18~24GHz頻段的低雜訊放大器，主要是用串接架構與回授式架構。透過串接與回授式架構可提高電路增益，輸入與輸出匹配則使用電容與電感來達成。此電路模擬之增益為19.11~20.64dB，輸入反射係數為-10.28~-32.99dB，輸出反射係數為-11.1~-49.04dB，隔離度為-44.55~-52.65dB，雜訊指數為2.64~2.99dB。

第二部分在相同頻率範圍下對低雜訊放大器布局(Layout)改善設計，因為先前在量測時結果不理想，並在布局改善接地與供應電源部分。此電路模擬之增益為13.2~15.35dB，輸入反射係數為-10.02~-50.65dB，輸出反射係數為-10.27~-46.15dB，隔離度為-35.54~-45.25dB，雜訊指數為2.52~2.99dB。

This papered studies the low noise amplifier (LNA) circuit of the 18 ~ 24GHz frequency band. The low noise amplifier plays an important role in the RF transceiver. While receiving the signal, it should have good gain, stability, and low noise at output. This circuit uses a cascade design. The first stage of the circuit is mainly based on low noise and good input matching. The second and third stages are to improve the circuit gain and stability through cascade and feedback, to reach good gain, stability and low noise.

In this study, WIN Semiconductors Corp's 0.15um pHEMT process was used to implement the circuit. The simulation and measurement results and compared.

The first part is to design a low noise amplifier in the 18 ~ 24GHz frequency band, which mainly uses a cascade architecture and a feedback architecture. Through the cascade and feedback architecture, the circuit gain can be improved. The input and output matching is achieved by using capacitors and inductors. The simulated circuit gain is 19.11 ~ 20.64dB, the input reflection coefficient is -10.28 ~ -32.99dB, the output reflection coefficient is -11.1 ~ -49.04dB, the isolation is -44.55 ~ -52.65dB, and the noise figure is 2.64 ~ 2.99dB.
 
The second part is the improved design of this 18~24GHz low noise amplifier layout, because the results of the previous measurement are not ideal. The Layout are improved in the grounding and power supply parts. The simulated circuit gain is 13.2 ~ 15.35dB, the input reflection coefficient is -10.02 ~ -50.65dB, the output reflection coefficient is -10.27 ~ -46.15dB, the isolation is -35.54 ~ -45.25dB, and the noise figure is 2.52 ~ 2.99dB.

摘要……i
Abstract……ii
誌謝……iv
目錄……v
表目錄……vii
圖目錄……viii
第一章 緒論……1
1.1研究背景……1
1.2研究目的……2
1.3章節介紹……2
第二章 基本原理……3
2.1簡介……3
2.2散射參數(Scattering Parameters)……3
2.3雜訊指數(Noise Figure；NF)……5
2.3.1雜訊因子(Noise Factor；F)……5
2.3.2熱雜訊(Thermal Noise)……6
2.3.3散射雜訊(Shot Noise)……7
2.3.4閃爍雜訊(Flicker Noise)……8
2.3.5高電場擴散雜訊(High Field Diffusion Noise)……9
2.3.6等效雜訊溫度(Equivalent Noise Temperature)……10
2.3.7多級放大器雜訊計算……12
2.4線性度(Linearity)……13
2.4.1 1dB增益壓縮點(1dB Compression Point, P1dB)……13
2.4.2第三階截止點IIP3(Input 3rd-Order Intercept Point, IIP3)……15
2.5穩定度(Stability)……16
2.6 0.15μm pHEMT小訊號模型……18
2.7低雜訊放大器架構……19
2.7.1串接式架構(Cascade Architecture)……19
2.7.2疊接式架構(Cascode Architecture)……20
2.7.3回授式放大器(Feedback Amplifier)……21
2.7.4電流再利用架構(Current-Reuse Construction)……21
2.7.5源極電感退化式寬頻放大器(Inductive Source Degeneration)……22
2.7.6散佈式放大器(Distribute Amplifier)……22
第三章 18~24GHz頻段低雜訊放大器設計……23
3.1設計目的……23
3.2設計流程……23
3.3電路設計……25
3.4模擬結果……27
3.5結果與討論……32
第四章 18~24GHz低雜訊放大器布局重新設計……33
4.1設計目的……33
4.2電路設計……33
4.3模擬結果……34
4.4結果與討論……39
第五章 結論與未來展望……39
參考資料……40
Extended Abstract……42

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