[1]G. E. Moore, “Cramming more components onto integrated circuits”, Electronics. vol. 38, no. 8, Apr. 1965.
[2]C. S. Taillefer, et al., “Delta–Sigma A/D conversion via time-mode signal processing” IEEE Trans. Circuits Syst. I, vol. 56, no. 9, pp. 1908–1920, Sep. 2009.
[3]G. W. Roberts, et al., “A Brief Introduction to Time-to-Digital and Digital-to-Time Converters” IEEE Trans. Circuits Syst. II, vol. 57, no. 3, pp. 153–157, Mar. 2010.
[4]T. Okayasu, et al., “1.83 ps-Resolution CMOS dynamic arbitrary timing generator for ATE applications” IEEE ISSCC, pp. 2122-2131, Feb. 2006.
[5]B. Arkin, “Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers,” IEEE ISSCC, 2004, pp. 348–349.
[6]N. Pavlovic, et al., “A 5.3 GHz digital-to-time-converter based fractional-N all-digital PLL,” IEEE ISSCC, 2011, pp. 54–56.
[7]D. Tasca, et al., “A 2.9-to-4.0 GHz fractional-N digital PLL with bang-bang phase detector and 560 fs rms integrated jitter at 4.5 mW power,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2745–2758, Dec. 2011.
[8]N. Markulic, et al., “A 10-bit 550-fs step digital-to-time converter in 28 nm CMOS,” ESSCIRC, 2014, pp. 79–82.
[9]Anil Chawda, et al., “High Resolution Digital-to-Time Converter for Low Jitter Digital PLLs,” IEEE ICECS, 2014, pp. 25–28.
[10]T.-I. Otsuji, et al., “A 3-ns range, 8-ps resolution, timing generator LSI utilizing Si bipolar gate array,” IEEE J. Solid-State Circuits, vol. 26, no. 5, pp. 806–811, May 1991.
[11]S. Ai-Ahdab, et al., “A 12-Bit Digital-to-Time Converter (DTC) for Time-to-Digital Converter (TDC) and Other Time Domain Signal Processing Applications,” in Proc. NORCHIP, 2010, pp. 1–4.
[12]Bindi Wang, et al., “A Digital-to-Time Converter with Fully Digital Calibration Scheme for Ultra-Low Power ADPLL in 40 nm CMOS,” IEEE ISCAS, 2015, pp. 2289–2292.
[13]S. Talwalkar, et al., “Controlled dither in 90 nm digital to time conversion based direct digital synthesizer for spur mitigation,” IEEE RFIC Symp., 2010, pp. 23–25.
[14]J. Kalisz, et al., “A simple, precise, and low jitter delay/gate generator,” Rev. Sci. Instrum., vol. 74,no. 7, pp. 3507–3509, July 2003.
[15]P. Kwiatkowski, et al., “Accurate and low jitter time-interval generators based on phase shifting method,” Rev. Sci. Instrum., vol. 83, no. 3, pp. 034701(1–4), Mar. 2012.
[16]K. Klepacki, et al., “Low-jitter wide-range integrated time interval/delay generator based on combination of period counting and capacitor charging,” Rev. Sci. Instrum., vol. 86, no. 2, pp. 025111(1–7), Feb. 2015.
[17]J. A. Gasbarro, et al., “Integrated Pin Electronics for VLSI Functional Testers,” proc. IEEE CICC, 1989, pp. 331–337.
[18]G. Nagaraj, et al., “A self-calibrating sub-picosecond resolution digital-to time converter,” IEEE MTT-S Int. Microwave Symp., 2007, pp. 2201–2204.
[19]J. Z. Ru, et al., “A High-Linearity Digital-to-Time Converter Technique Constant-Slope Charging,” IEEE J. Solid-State Circuits, vol. 50, no. 6, pp. 1417–1423, June 2015.
[20]J. Chapman, “High performance CMOS based VLSI testers: timing control and compensation” IEEE International Test Conference, pp.59-67, 1992.
[21]Y. –C. Choi, et al., “A Fully Digital Polar Transmitter Using a Digital-to-Time Converter for High Data Rate System” IEEE RFIT, pp.56–59, 2009.
[22]T. Otsuji, et al., “A 10-ps resolution, process-Insensitive timing generator IC” IEEE J. Solid-State Circuits, vol. 24, no.10, pp.1412–1417, Oct. 1989.
[23]J. Christiansen, “An integrated high resolution CMOS timing generator based on an array of delay locked loops“ IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 952–957, Jul. 1996.
[24]P. Chen, et al., “A FPGA Vernier Digital-to-Time Converter with 3.56ps Resolution and -0.23~+0.2LSB Inaccuracy” IEEE CICC, pp. 209–212, Sept. 2008.
[25]C. Branson, “Integrated Pin Electronics for a VLSI test system” IEEE Trans. On Industrial Electronics, Vol. 36, No.2, MAY.1989.
[26]P. Chen, et al., “FPGA Vernier Digital-to-Time Converter With 1.58 ps Resolution and 59.3 Minutes Operation Range” IEEE Trans. Circuits Syst. vol. 57, no. 6, June 2010.
[27]B. B. Robbins, et al., “Low cost timing generator for automatic test equipment operating at high data rates” U.S Patent ,No.5566188 Oct.15,1996
[28]張凱翔,2019,內建偏移誤差消除之CMOS脈衝縮減式時間至數位轉換器,國立高雄科技大學,碩士論文。[29]M. M. MANO, “DIGITAL DESIGN.” Third edition, Prentice Hall, Inc., 2002.
[30]P. Chen, et al., “A CMOS pulse-shrinking delay element for time interval measurement,” IEEE Trans. Circuits Syst. II, vol. 47 no. 9, pp. 954–958, Sep. 2000.
[31]C. Chen, et al., “All-Digital Cost-Efficient CMOS Digital-to-Time Converter Using Binary-Weighted Pulse Expansion” IEEE Trans. VLSI Syst. vol. 28 no. 4, pp. 1094–1098, Apr. 2020.
[32]T. Ouyang, et al., “A high resolution Time-to-Digital Converter (TDC) based on self-calibrated Digital-to-Time Converter (DTC)” IEEE MWSCAS Int., 2017, pp. 675–678.
[33]尤松泉,2018,具自動曲率校正之高精度全數位智慧型溫度感測器之設計與實作,國立高雄科技大學,碩士論文。[34]LD1117/A Low Drop Fixed And Adjustable Positive Voltage Regulators, UNISONIC TECHNOLOGIES CO
[35]TXB0104-Q1 4-Bit Bidirectional Voltage-Level Translator with Automatic Direction Sensing and ±15-kV ESD Protection, TEXAS INSTRUMENTS
[36]X. Meng, et al., “Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS” IEEE Trans. VLSI Syst. vol. 16, no. 11, Nov 2008.
[37]C. Chen, et al., "All-digital pulse-expansion-based CMOS digital-to-time converter", Rev. Sci. Instrum., vol. 88, no. 2, Feb. 2017.
[38]T.-Y. Wang, et al., “Multiple channel programmable timing generators with single cyclic delay line,” IEEE Trans. Instrum. Meas., vol. 53, pp. 1295–1303, Aug. 2004.
[39]劉秉竑,2016,具二進制權重機制之CMOS數位至時間轉換器,國立高雄科技大學,碩士論文。[40]C.-C. Chen, et al., “CMOS time-to-digital converter based on a pulse-mixing scheme” Review of Scientific Instruments, vol. 85, no. 11, pp. 114702(1-9), 2014.