臺灣博碩士論文加值系統

本論文提出三種不同架構之差動式BiCMOS參考電壓電路。利用不同的電路元件與製程參數組成數種不同電路型態，進而探討哪種電路具備更好的成效。第一類電路是透過單一BJT之負溫度係數特性與MOSFET臨界電壓之負溫度特性所產生；第二類電路是利用單一BJT之負溫度係數特性與BJT之基射極接面電壓差(ΔVBE)產生的正溫度係數特性搭配產生；第三類是透過兩對BJT之基射極接面電壓差(ΔVBE)產生的正溫度係數特性所產生，以上三種不同型式，皆以適當的權重值將溫度係數相互抵消來實現具有零溫度係數特性的參考電壓。

本論文使用TSMC 0.35微米以及TSMC 0.18微米製程參數進行晶片佈局，並利用HSPICE與ADE(Analog Design Environment)電路模擬軟體進行pre-sim與post-sim的模擬，並經由實作晶片進行量測；相較於現有的參考電壓電路，本論文提出之差動輸出參考電壓電路具有更實用的輸出電壓值與更小的功率消耗，符合低功率消耗與低供應電壓的產品設計趨勢，且本電路不需使用運算放大器，電路架構簡單，並利用較少的晶片面積，節省製造成本。佈局前後模擬結果皆與設計理論相符合，證明電路的正確性與可行性。本論文提出之差動輸出參考電壓電路可作為電路模組應用於各種相關之類比與混合模式積體電路設計之中。

In this thesis, We have proposed three different type of BiCMOS differential-mode reference voltage. Using different circuit components and process parameters to implement a number of different circuit types, explore which type of circuits is more effective. In order to realize the zero temperature-coefficient, the first circuit uses the negative temperature-coefficient of the BJT junction voltage and the threshold voltage of the MOSFET to cancel each other. Similarly, it can also be realized by using the negative temperature-coefficient given from a BJT and the positive temperature-coefficient obtained from the voltage difference of two base-to-emitter voltage of the BJT. Finally, the third circuit demonstrates that the zero temperature-coefficient can be reached by subtracting two positive temperature-coefficients given from two different junction voltages of the BJT pairs.

The chip layout of the proposed differential-mode reference voltage have been made with 0.35μm and 0.18μm process parameters. The HSPICE and ADE (Analog Design Environment) simulation programs have been used to perform the pre-layout and post-layout simulation. Comparing with the existed reference voltage circuits, the proposed circuit do not need to use any operational amplifier therefore they benefits from simpler circuit architecture, less chip area, and thus reducing the production cost dramatically. All the simulation results of the proposed differential mode output reference voltages are consistent with the theoretic analysis which confirms the feasibility of the proposed circuits. The proposed differential mode output reference voltages can be applied to different analog and mix-mode integrated circuits as circuit modules.

摘要.....i
Abstract.....ii
誌謝.....iii
目錄.....iv
表目錄.....vi
圖目錄.....vii
符號說明.....xii
第一章 緒論.....1
1.1積體電路產業的背景與趨勢.....1
1.2研究動機與目的.....2
1.3研究方向與重點.....3
1.4論文架構簡介.....3
1.5設計流程.....3
第二章 傳統參考電壓電路.....5
2.1參考電壓簡介.....5
2.2參考電壓工作原理.....5
2.3 BJT參考電壓電路架構.....7
2.3.1 負溫度係數特性.....7
2.3.2 正溫度係數特性.....9
2.3.3 BJT參考電壓電路....9
2.4 MOSFET參考電壓電路架構.....10
2.4.1 次臨界區與溫度特性...10
2.4.2 MOSFET 參考電壓電路......12
第三章 差動式BiCMOS參考電壓設計實務.....13
3.1 CMOS差動輸出參考電壓電路.....14
3.2 第一種差動式BiCMOS參考電壓電路.....15
3.2.1第一種差動式BiCMOS參考電壓電路分析.....15
3.2.2第一種差動式BiCMOS參考電壓電路模擬與佈局.....16
3.3 第二種差動式BiCMOS參考電壓電路.....19
3.3.1第二種差動式BiCMOS參考電壓電路分析.....15
3.3.2第二種差動式BiCMOS參考電壓電路模擬與佈局.....19
3.4 第三種差動式BiCMOS參考電壓電路.....22
3.4.1第三種差動式BiCMOS參考電壓電路分析.....22
3.4.2第三種差動式BiCMOS參考電壓電路模擬與佈局.....24
3.5 第四種差動式BiCMOS參考電壓電路.....27
3.4.1第四種差動式BiCMOS參考電壓電路分析.....27
3.4.2第四種差動式BiCMOS參考電壓電路模擬與佈局.....27
3.6 第五種差動式BiCMOS參考電壓電路.....30
3.6.1第五種差動式BiCMOS參考電壓電路分析.....30
3.6.2第五種差動式BiCMOS參考電壓電路模擬與佈局.....30
3.7 第六種差動式BiCMOS參考電壓電路.....33
3.7.1第六種差動式BiCMOS參考電壓電路分析.....33
3.7.2第六種差動式BiCMOS參考電壓電路模擬與佈局.....35
3.8 第七種差動式BiCMOS參考電壓電路.....38
3.8.1第七種差動式BiCMOS參考電壓電路分析.....38
3.8.2第七種差動式BiCMOS參考電壓電路模擬與佈局.....38
3.9 第八種差動式BiCMOS參考電壓電路.....41
3.9.1第八種差動式BiCMOS參考電壓電路分析.....42
3.9.2第八種差動式BiCMOS參考電壓電路模擬與佈局.....42
3.10 第九種差動式BiCMOS參考電壓電路.....45
3.10.1第九種差動式BiCMOS參考電壓電路分析.....45
3.10.2第九種差動式BiCMOS參考電壓電路模擬與佈局.....45
3.11九種差動式BiCMOS參考電壓電路模擬結果與討論.....49
第四章 晶片實作與量測結果.....51
4.1 全客製化IC設計流程.....51
4.2 量測儀器與流程.....53
4.3 第一種差動式BiCMOS參考電壓電路實體與量測結果.....54
4.3.1 晶片實體.....54
4.3.2 晶片量測結果.....55
4.4 第二種差動式BiCMOS參考電壓電路實體與量測結果.....60
4.4.1 晶片實體.....61
4.4.2 晶片量測結果.....61
4.5 第三種差動式BiCMOS參考電壓電路實體與量測結果.....66
4.5.1 晶片實體.....66
4.5.2 晶片量測結果.....67
4.6 第四種差動式BiCMOS參考電壓電路實體與量測結果.....72
4.6.1 晶片實體.....72
4.6.2 晶片量測結果.....73
4.7 第五種差動式BiCMOS參考電壓電路實體與量測結果.....78
4.7.1 晶片實體.....78
4.7.2 晶片量測結果.....79
4.8 第六種差動式BiCMOS參考電壓電路實體與量測結果.....84
4.8.1 晶片實體.....84
4.8.2 晶片量測結果.....85
4.9 第七種差動式BiCMOS參考電壓電路實體與量測結果.....90
4.9.1 晶片實體.....90
4.9.2 晶片量測結果.....91
4.10第八種差動式BiCMOS參考電壓電路實體與量測結果.....96
4.10.1 晶片實體.....96
4.10.2 晶片量測結果.....97
4.11第九種差動式BiCMOS參考電壓電路實體與量測結果.....102
4.11.1 晶片實體.....102
4.11.2 晶片量測結果.....103
第五章 結論與討論.....108
參考文獻.....111
Extended Abstract.....114

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