在2009年美國聯邦通訊委員會制定了一個工作頻率範圍在401~406MHz的無線頻帶供作醫療裝置無線通訊服務，其中402~405MHz是植入式醫療裝置所使用的範圍，401~402MHz和405~406MHz是穿戴式醫療裝置所使用的範圍。其應用的範圍適合在具有極低功耗和在短距離下有更快速的資料傳輸速度的完全積體化之人體植入式電子輔具。
本論文設計了一個應用於植入式視覺輔具之開迴路調變頻率合成器，並提出一種新架構的調變方法，能有低電路複雜度和快速資料傳輸速度的優點，那是使用開迴路系統架構和在迴路濾波器與壓控振盪器中間加入一組類比加法器，藉由改變類比加法器的控制開關而直接改變壓控振盪器所需的控制端電壓以達到直接調變的方式。在壓控振盪器的設計，利用降低金屬繞線電感之寄生電阻而增加品質因素以及使用可調電容來降低壓控振盪器KVCO值的方式來改善壓控振盪器的相位雜訊。
最後使用TSMC 0.18μm 1P6M CMOS標準製程來實現此開迴路調變頻率合成器，工作電壓為1.5V，晶片面積為1.995 mm2。在佈局的模擬結果可以看到壓控振盪器的相位雜訊在距離載波160kHz處為-106.7dBc/Hz，總可調範圍為85MHz；而調變頻率合成器鎖定時間小於50μs，消耗功率為2.89mW，資料傳輸速度可達1Mbps。

In 2009, the US Federal Communication Commission (FCC) announced that Medical Device Radiocommunication Service (MedRadio) band is in the range of 401-406MHz, where 402-405MHz band is for medical implant devices, and 401-402MHz and 405-406MHz bands are for usages of medical body-worn devices. The application of MedRadio band is suitable for fully integrated human implantable prostheses with ultra-low power consumption and higher data rate in a short distance.
In order to implement an available frequency synthesizer with open-loop BFSK modula-tion for implantable visual prostheses, this thesis mainly proposes a new modulation circuit that features low complexity and high data rate. Using open-loop modulation with an analog adder to the LPF before the VCO, the proposed circuit achieves the mechanism of direct modulation by switching input the voltage level of the analog adder to adjust the input voltage of the VCO. Besides, the design of VCO reduces parasitic resistance of metal spiral inductor and lowers the KVCO of VCO to improve the phase noise of VCO.
The designed circuits in this thesis are implemented in TSMC 0.18 μm standard CMOS process with 1.5V supply voltage, and the chip area is 1.995 mm2. The post-layout-simulation results show that -106.7 dBc/Hz of VCO phase noise at 160 kHz offset, less than 50 μs of locking time, 2.89 mW of power consumption, and 1 Mbps of data rate are achieved in the designed frequency synthesizer.

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 3
1.3 論文架構 5
第二章 鎖相迴路與調變頻率合成器之基本理論 6
2.1 鎖相迴路組成元件介紹 6
2.1.1 壓控振盪器 7
2.1.2 除頻器 13
2.1.3 相位頻率偵測器 15
2.1.4 電荷幫浦 16
2.1.5 迴路濾波器 18
2.2 鎖相迴路原理分析 19
2.2.1 線性數學模型理論 19
2.2.2 鎖相迴路的行為性模擬 23
2.3 調變頻率合成器介紹 26
2.3.1 開迴路系統架構 26
2.3.2 閉迴路系統架構 27
第三章 調變電路之實現 28
3.1 調變方法介紹 28
3.2 類比加法器架構 29
3.3 電荷幫浦致能電路 34
第四章 頻率合成器之實現 37
4.1 壓控振盪器 38
4.1.1 電感品質因數的提升 39
4.1.2 相位雜訊及功率上的最佳化 40
4.2 除頻器 42
4.3 相位頻率偵測器 43
4.4 電荷幫浦 45
4.5 迴路濾波器 46
第五章 電路模擬與晶片量測 49
5.1 壓控振盪器之模擬結果 49
5.2 頻率合成器之模擬結果 52
5.3 晶片佈局 56
5.4 電路量測 58
5.4.1 量測考量 58
5.4.2 量測結果與討論 61
第六章 結論 69
6.1 結論 69
6.2 未來展望 70
參考文獻 71

[1]FCC Rules and Regulations, “MedRadio Band Plan,” Part 95, Oct. 2009.
[2]Federal Communications Commission, Operations of Med Radio, Sept. 2009, http://wireless.fcc.gov/services/index.htm?job=operations&id=medical_implant
[3]T. Melly, A.-S. Porret, C. C. Enz, E. A. Vittoz, “An ultralow-power UHF transceiver integrated in a standard digital CMOS process: transmitter,” IEEE Journal of Solid State Circuits, vol. 36, pp. 467-472, Aug. 2001.
[4]M.H. Perrott, T.L. Tewksbury III, C.G. Sodini, “A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation,” IEEE Journal of Solid State Circuits, vol. 32, pp. 2048-2060, Dec. 1997.
[5]Y.-H. Liu, T.-H. Lin, “A Wideband PLL-Based G/FSK Transmitter in 0.18 um CMOS,” IEEE Journal of Solid State Circuits, vol. 44, pp. 2452-2462, Sept. 2009.
[6]Fairchild Semiconductor Application Note 340, “HCMOS Crystal Oscillators,” May 1983.
[7]J. Rogers, C. Plett, F. Dai, Integrated circuit design for high-speed frequency synthesis. Boston : Artech House, Jan. 2006.
[8]B. Razavi, RF Mcroelectronics. Upper Saddle River, NJ: Prentice Hall, 1998.
[9]A. Hajimiri, T. H. Lee, “Phase noise in CMOS differential LC oscillators,” IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 48-51, Jun. 1998.
[10]A. Hajimiri, T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE Journal of Solid State Circuits, vol. 33, pp. 179-194, Feb. 1998.
[11]J. Rogers, C. Plett, F. Dai, Integrated circuit design for high-speed frequency synthesis. Boston: Artech House, Jan. 2006.
[12]B. Razavi, “A study of injection locking and pulling in oscillators,” IE EE Journal of Solid State Circuits, vol. 39, pp. 1415-1424, Sept. 2004.
[13]S. B. Sleiman, J. G. Atallah, S. Rodriguez, A. Rusu, M. Ismail, “Wide-division-range high-speed fully programmable frequency divider,” in the Annual IEEE Northeast Workshop on Circuits and Systems, pp. 17-20, Jun. 2008.
[14]H.O. Johansson, “A simple precharged CMOS phase frequency detector,” IEEE Journal of Solid State Circuits, vol. 33, no.2, pp. 295-299, Feb. 1998.
[15]W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” IEEE International Symposium on Circuits and Systems, vol.2, pp. 545-548, Jul. 1999.
[16]彭康峻, “無線通訊分數式頻率合成器之現場可程式化邏輯陣列電路設計,” 國立中山大學電機工程研究所碩士論文, 2000.
[17]W. Rahajandraibe, L. Zaid, V. Cheynet de Beaupre, G. Bas. “Frequency Synthesizer and FSK Modulator for IEEE 802.15.4 Based Applications,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 229-232, June 2007.
[18]F. Jonsson, H. Olsson, “A Low-Leakage Open-Loop Frequency Synthesizer Allowing Small-Area On-Chip Loop Filter,” IEEE Transactions on Circuits and Systems, vol. 56, pp. 195-199, March 2009.
[19]B. Miller, R. J. Conley, “A multiple modulator fractional divider,” IEEE Transactions on Instrumentation and Measurement, vol. 40, no. 3, pp. 578-583, Jun. 1991.
[20]B. Razavi, Design of Analog CMOS Integrated Circuits. International Edition 2001, McGraw 2001
[21]A. Hajimiri, T. H. Lee, The Design of Low Noise Oscillators. Boston: Kluwer Academic, 2003.
[22]R. J. Kier, R. R. Harrison, “Power minimization of a 433-MHz LC VCO for an implantable neural recording system,” IEEE International Symposium on Circuits and Systems, pp. 3225-3228, Sept. 2006.
[23]C.-C. Hsiao, C.-W. Kuo, C.-C. Ho, Y.-J. Chan, “Improved quality-factor of 0.18um CMOS active inductor by a feedback resistance design,” IEEE Microwave and Wireless Components Letters, vol. 12, pp. 467-469, Dec. 2002.
[24]C.-H. Wu, C.-Y. Kuo, S.-I. Liu, “Selective metal parallel shunting inductor and its VCO application,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, pp. 1811-1818, Sept. 2005.
[25]A. Hajimiri, T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE Journal of Solid State Circuits, vol. 34, pp. 717-724, May 1999.
[26]R. Caverly, CMOS RFIC Design Principles. Norwood: Artech House, 2007.
[27]A. D. Berny, A. M. Niknejad, R. G. Meyer, “A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration,” IEEE Journal of Solid State Circuits, vol. 40, pp. 909-917, Apr. 2005.
[28]T.-H. Lin, W. J. Kaiser, “A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop,” IEEE Journal of Solid State Circuits, vol. 36, pp. 424-431, Mar. 2001.
[29]C.-S. A. Gong, M.-T. Shiue, K.-W. Yao, T.-Y. Chen, Y. Chang ; C.-H. Su, “A Truly Low-Cost High-Efficiency ASK Demodulator Based On Self-Sampling Scheme for Bioimplantable Applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, pp. 1464-1477, Jul. 2008.
[30]N. Boom, W. Rens, and J. Crols, “A 5.0mW 0dBm FSK transmitter for 315/433 MHz ISM applications in 0.25um CMOS,” in Proc. the 29th European Solid-State Circuits Conf. (ESSCIRC''04), pp. 199-202, Sept. 2004.
[31]Y.-H. Liu, C.-J. Tung, and T.-H. Lin, “A Low-Power Asymmetrical MICS Wireless Interface and Transceiver Design for Medical Imaging,” IEEE Biomedical Circuits and Systems Conference, pp. 162-165, Dec. 2006.
[32]K.-C. Liao, P.-S. Huang, W.-H. Chiu, and T.-H. Lin, “A 400-MHz/900-MHz/2.4-GHz Multi-band FSK Transmitter in 0.18-µm CMOS,” IEEE Asian Solid-State Circuits Conference, pp. 353-356, Nov. 2009.
[33]V. Karam, P.H.R. Popplewell, A. Shamim, J. Rogers, and C. Plett, “A 6.3 GHz BFSK Transmitter with On-Chip Antenna for Self-Powered Medical Sensor Applications,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 101-104, June 2007.
[34]高曜煌, “射頻鎖相迴路IC設計,” 滄海書局, 2005.
[35]劉深淵,楊清淵, “鎖相迴路,” 滄海書局, 2006.