臺灣博碩士論文加值系統

近來，NAND型快閃記憶體已成為目前最主流的儲存記憶體，並廣泛地被運用於各種攜帶式的電子產品上，例如手機、筆記型電腦以及固態硬碟。與此同時，製造商也藉由縮小NAND型快閃記憶體的製程以及讓每個單位(Cell)儲存更多位元(Bit)來達到降低成本的目的；然而，卻也使得快閃記憶體的可靠度及耐久度出現嚴重衰減的問題。寫入干擾(Program Interference)是可靠度的降低下的一個重要因素，發生於儲存在單位裡的電壓因受鄰近單位寫入電壓影響而往高電壓的方向移動。另一方面，保存錯誤（Retention Error）則是由於已存有資料的單位經過一段長時間後造成儲存電壓往低電壓的方向移動。在這篇論文中，我們透過實驗儀器來量測19奈米的NAND型快閃記憶體，並安排了各種模擬環境藉以觀察NAND型快閃記憶體的錯誤特性。此外，我們還建立了簡易的電壓估計策略，並探討足以判定儲存電壓老化程度的參考訉號(Pilot)之最小數量。

Recently, NAND flash memory has been the mainstream of storage medium for portable consumer electronic devices, such as mobile phone, laptop and solid state disk (SSD). Meanwhile, manufacturers are striving to reduce the cost by scaling down to smaller process and storing more bits in each cell for NAND flash memory. Therefore, the reliability and endurance of flash memory are seriously degraded. One important issue of reduced reliability is program interference that happens when the voltage stored in a cell shifts toward the positive direction while the neighbouring cells are programmed. On the other hand, retention error leads to voltage shift toward the negative direction after storing data in a cell for a long time. In this paper, we develop experiment instrument for the measurement of 19 nm NAND flash memory. We setup simulation environments and observe error characteristic of the NAND flash memory. Besides, we develop simple voltage estimation strategy and discuss the minimum required number of pilots to determine the aging of the stored voltage.

Abstract
Acknowledgements
Contents
1 Introduction
1.1 Error Characterization for NAND Flash Memory

2 SDK Controller and Interface
2.1 SDK Interface

3 Program Interference Error Experimental Method and Results
3.1 Bit-Line to Bit-Line Program Interference
3.2 Word-Line to Word-Line Program Interference

4 Retention Error Experimental Method and Results
4.1 Compare Retention Error for TLC 8-Level with Different P/E and Different
Bake time
4.2 Put Different Amount of Pilot with Different Confidence Level for TLC
8-Level
4.3 Estimation Retention Time with Different Amount of Pilot

5 Conclusions

[1]Yu Cai, Erich F. Haratsch, Onur Mutlu, and Ken Mai, “Error patterns in MLC NAND flash memory: measurement, characterization, and analysis,” Design, Automation & Test in Europe Conference & Exhibition (2012), pp. 521-526, MAR. 12-16 (2012).

[2]Eitan Yaakobi, J. Ma, L. Grupp, P. H. Siegel, S. Swanson, and J. K. Wolf, “Error Characterization and Coding Schemes for Flash Memories,” in Proc. Of GLOBECOM Workshops (GC Wkshps 2010), pp. 1856-1860, Miami, USA, Dec. 2010.

[3]J. Wang, T. Courtade, H. Shanker, and R. D. Wesel, “Soft information for LDPC decoding in flash: Mutual-Information Optimized Quantization,” in Proc. Of Global Telecommunication Conference (GLOBECOM 2011), pp. 1-6, Houston, TX, USA, Dec. 2011.

[4]P. H. Chen, J. J. Weng, C. H. Wang, and P. N. Chen, “BCH code selection and iterative decoding for BCH and LDPC concatenated coding system,” IEEE Commun. Lett., vol. 17, no. 5, pp. 980-983, May. 2013.

[5]Yu Cai, Erich F. Haratsch, Onur Mutlu, and Ken Mai, “Program Interference in MLC NAND Flash Memory : Characterization , Modeling , and Mitigation” Computer Design (ICCD), 2013 IEEE 〖31〗^st International Conference on, pp. 123-130, Oct. 2013.

[6]D. H. Lee, and W. Sung, “Estimation of NAND Flash Memory Threshold Voltage Distribution for Optimum Soft-Decision Error Correction,” IEEE Trans. Signal Process., vol. 61, no. 2, pp. 440-449, Jan. 2013.

[7]G. Dong, Y. Pan, N. Xie, C. Varanasi, and T. Zhang, “Estimating Information - Theoretical NAND Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration,” IEEE Trans. VLSI Syst., vol. 20, no. 9, pp. 1705-1714, Sep. 2012.

[8]P. Newbold, W. L. Carlson and B. Thorne. (2009). Statistics for Business and the Economics, 7^th Edition, Pearson.