臺灣博碩士論文加值系統

本論文呈現一個低電壓/低功率三階低通三角積分調變器，可應用於音頻應用上，信號頻率為4KHz，此頻率為一般人說話的聲音頻率。由於可攜性的考量，而電池的選取對於可攜式產品是相當重要的，因此本調變器使用單端電源為1.8V，可有效降低電池重量，適合用於有輕便性需求的產品上。在超取樣率為64時，所得到的解析度約為8-bit，且其頻寬為8KHz。本調變器的佈局面積為991 um×991um，使用台積電0.35um 2P4M的製程去實現。
此三角積分調變器使用超取樣及1-bit的量化器去達到較高解析度的類比轉數位調變器，由於1-bit量化器的輸出只有兩個值，即0或1，因此在製作期間不需要額外的調整。使用三角積分調變器技術為基礎的超取樣低通類比數位轉換器有著不少的優點，如：較能被依賴，隨著製程能夠增加效能，並且還能有效降低低頻雜訊及避免直流偏移。

This paper presents a low-voltage/low-power MASH 1-1-1 sigma-delta modulator for voice band of 4KHz with a bandwidth of 8KHz. The modulator operates in a 1.8V power supply; the involved operational amplifiers dissipate only 56W. The OSR is 64, and area is 991um×991um. The modulator is implemented in TSMC035 2P4M process and the resulting resolution is about 8 bits.
The sigma-delta modulator uses oversampling and 1-bit quantization to achieve high resolution A/D conversion at a lower rate. The 1-bit quantizer’s output of the sigma-delta modulator is essentially of two values, and hence needs no extra adjustment during manufacturing. In the analog-to-digital converter, the integrator can be composed of operational amplifiers and switched capacitors, and in addition, a digital-to-analog converter is not required in the feedback path. Therefore, sigma-delta modulator features high performance, a small circuit scale, and the possibility of manufacturing. It employs the multistage noise shaping (MASH) modulation techniques without using higher order integrators.

1.1 MOTIVATION 3
1.2 ORGANIZATION 3
2.1 TECHNIQUES TO ACHIEVE HIGH-RESOLUTION 3
2.1.1 OVERSAMPLING 3
2.1.2 OVERSAMPLING THEORY 3
2.1.3 SIGNAL-TO-NOISE PLUS DISTORTION RATIO 3
2.1.4 DYNAMIC RANGE 3
2.1.5 NOISE SHAPING 3
2.2 ONE-BIT DAC 3
2.3 OVERSAMPLING A/D CONVERTERS 3
2.4 FIRST-ORDER ΣΔ MODULATORS 3
2.5 SECOND-ORDER ΣΔ MODULATORS 3
2.6 HIGHER-ORDER ΣΔ MODULATORS 3
2.6.1 INTERPOLATIVE ARCHITECTURE 3
2.6.2 CASCADED ΣΔ MODULATORS 3
2.7 MULTIBIT ΣΔ MODULATORS 3
2.8 DESIGN CHOICE FOR MODULATOR ARCHITECTURE 3
3.1 TOWARDS LOW SUPPLY VOLTAGE 3
3.1.1 TECHNOLOGY SCALING IN CMOS PROCESSES 3
3.1.2 LIMITATIONS OF SC CIRCUIT AT LOW VOLTAGE 3
3.1.3 LEAKAGE CURRENT 3
3.1.4 NOISE CONSIDERATION 3
3.2 SC INTEGRATORS AT LOW VOLTAGE 3
3.2.1 LIMITATION OF SWITCHES 3
3.2.2 VOLTAGE MULTIPLIERS 3
3.2.3 CLOCK BOOTSTRAPPED SWITCHES 3
3.2.4 LOW-VT PROCESS 3
3.2.5 SWITCHED-OPAMP TECHNIQUE 3
3.3 LOW-VOLTAGE SWITCHED-CAPACITOR CIRCUITS 3
4.1 DESIGN FLOW 3
4.2 DESIGN CONSIDERATION 3
4.2.1 NTF DESIGN 3
4.2.2 SIGNAL SCALING 3
4.2.3 CHARGE INJECTION ERRORS 3
4.2.4 FINITE OPAMP GAIN EFFECT 3
4.2.5 NOISE RESTRICTIONS AT LOW VOLTAGES 3
4.2.6 NOISE IN INTEGRATED CIRCUITS 3
4.2.6.1 MOS TRANSISTOR 3
4.3 SIMULATION RESULT BY SIMULINK 3
4.3.1 SIMULATION RESULT OF THE FIRST-ORDER MODULATOR 3
4.3.2 THE SYSTEM ARCHITECTURE OF MASH 1-1-1 3
4.4 SIMULATION RESULT WITH IDEAL OPAMP BY SWITCAP2 3
4.5 SIMULATION RESULT BY HSPICE 3
5.1 CLASS AB FULLY-DIFFERENTIAL AMPLIFIER 3
5.2 COMPARATOR AND LATCH 3
5.3 NON-OVERLAPPING CLOCK GENERATOR 3
5.4 CLOCK BOOSTERS 3
5.5 BIAS CIRCUITS 3
5.6 SIMULATION OF SYSTEM CIRCUIT 3
5.6.1 FIRST-ORDER SIGMA-DELTA MODULATOR 3
5.6.2 THE MODULATOR OF MASH 1-1-1 3
6.1 PHYSICAL LAYOUT CONSIDERATION 3
6.1.1 MATCH OF CAPACITOR LAYOUT 3
6.2 SYSTEM SIMULATION RESULT BY HSPICE 3
6.2.1 SIMULATION RESULTS OF MASH 1-1-1 BY IDEAL OPAMP 3
6.2.2 SIMULATION RESULTS OF MASH 1-1-1 WITH REAL OPAMP 3
6.2.3 PHYSICAL LAYOUT AND POST-SIMULATION RESULTS OF MASH 1-1-1 3
6.3 MEASURE CONSIDERATION 3
6.3.1 MEASURE ARCHITECTURE 3
6.3.2 MEASURE STEP 3
7.1 SUMMARY 3
7.2 RECOMMENDATIONS FOR FURTHER INVESTIGATION 3

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