臺灣博碩士論文加值系統

由於行動裝置的普及，低功耗變成一個勢必達成的目標，因此，在IC設計中，業界及學術界頻頻研究有關於脈衝栓鎖器的研究，因為它與傳統的正反器比起來，它擁有較小的延遲時間和功率消耗，因此，以脈衝栓鎖器來取代正反器，可以增進電路的效能並降低功率，本論文提出一個演算法將脈衝栓鎖器加入電路中來有效的降低電路的功率消耗和增進效能，除此之外，傳統的脈衝寬度定義，是不適合用來解釋電路之時序行為，因此本論文提出一些脈衝寬度定義，發現一個以電壓10%至10%(vdd/gnd)及90%至90%(vdd/gnd)之脈衝寬度相乘再開根號之幾何平均根的定義是較合理的。

With wide use of mobile devices, low power consumption has became an ultimate goal. Hence, industry and academia propose using pulsed latches in IC design for power reduction. Pulsed latch has smaller delay time and low power consumption than flip-flop does. Therefore, pulsed latch is a good choice for timing element. In this thesis, we present a method to replace the flip-flops in a design by latches or pulsed latches in order to reduce power consumption. In addition, we also present several pulse width definitions. We find that it is more reasonable to define pulse width as the square root of the product of the duration from 90% supply voltage to 90% supply voltage and the duration from 10% to 10% supply voltage.

Chapter 1. Introduction 1
1.1. Background 1
1.2. Scope of the Work and Contribution 5
1.3. Thesis Organization 7
Chapter 2. Related Work 8
2.1. Pulse Generator and Pulsed Latch 8
2.2. Pulsed-Latch Aware Placement 12
2.3. Pulsed Latch Replacement from Cadence 13
2.4. Replace Two Latches by Using Retiming 15
Chapter 3. Studies of Pulsed Latches and Pulse Width Definitions 16
3.1. Studies of Pulsed Latch 16
3.2. Comparison of Flip-Flop and Pulsed Latch 20
3.3. Timing of Pulsed Latch Influenced by Bootstrapping 22
3.4. Timing Degradation of Wire Effect 26
3.5. Pulse Width Degradation due to Pulse Propagation 31
3.6. Issues about Pulse Width 33
Chapter 4. Methodology for Replacement of Flip-Flop 49
4.1. Timing Requirements for Replacement of Flip-Flops 52
4.2. Replacement Methods 55
Chapter 5. Experimental Result 62
Chapter 6. Conclusions 67
References 68

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