臺灣博碩士論文加值系統

因處理大量資料的需求，低耗電高處理速度的記憶體容量必須隨之增加，因此，為達到此一目的，動態隨機存取記憶體(Dynamic Random Access Memory , DRAM)元件的尺寸需不斷被微縮與提高效能。對於未來最新一代，且具有高密度的4F2 陣列DRAM而言，垂直結構的單元電晶體(cell transistor)是必須的。垂直式柱狀電晶體(Vertical pillar transistor ,VPT)因為具有非常好的閘極(gate)控制力而被認為是4F2陣列單元電晶體的最佳選擇。
垂直式柱狀電晶體，即位元線(Bit Line)與字元線(Word Line)埋入矽晶圓中，以達到製程尺寸微縮與封裝體積縮小為目的。為了將位元線與字元線埋入矽晶圓中(burry word and burry bit line)，目前的研究是先蝕刻出位元線的溝槽，後製程再將字元線的溝槽蝕刻出來，利用兩次不同的蝕刻製程來求得作為電晶體通道的矽柱狀體。所以利用電漿乾蝕刻矽溝槽將是本研究所要探討的主要重點。實驗以40nm的製程尺寸，改變不同的蝕刻參數，並觀察不同蝕刻參數對矽溝槽的圖形變化，以求得一垂直圖形(Vertical Profile)的矽溝槽為目的。
研究方法分為三個部分:
(1)以HBr為主蝕刻氣體，因為HBr對絕對尺寸(Critical dimension , CD)有很好的控制能力，研究中添加了Ar來幫助蝕刻，其結果不佳，得到了理想的CD與平坦的溝槽底部，但溝槽圖案猶如保齡球瓶(Bowing)。
(2)以SF6、CF4、CHF3、O2、N2...等的混和氣體，因SF6釋放出大量陰電性強的F離子，側向蝕刻嚴重，矽溝槽開口的CD不易控制。
(3)矽溝槽蝕刻步驟分成兩步: 1st trench Cl2/CF4/CHF3等混和氣體與2nd trench NF3/Cl2/CF4/CHF3等混和氣體，可以得到一最佳化的矽溝槽。

Due to the demand of large data processing, the low power consumption, high process speed and high capacitor of memory are increasing drastically. For this purpose, it is necessary to shrink the chip size of dynamic random access memory (DRAM) and improve the related functions. However, by physical limits, it is more difficult to scale down the transistors. For the new generation of high density 4F2 transistor, “Vertical Pillar Transistor (VPT)” with well control ability on “Gate”, VPT is one of the best choices for 4F2 array transistor.
For scaling down and low package bulk, VPT is a device that burying “Bit Line” and “Word Line” into silicon. For burying word/bit line process, etching bit line trench and then word line trench was carried out to get transistor channel (silicon pillar) in this study. Base on 40 nm process, a vertical profile of silicon trench may be achieved by adjusting etching parameters.
There are three different process were tried. (1) Due to its good critical dimension (CD) control ability, hydrogen bromide (HBr) was used as the primary etching gas. In this experiment, argon (Ar) is added in for ion bombard improvement. Although good CD control and flat bottom of silicon were derived, a bowing profile was observed. (2) SF6/CF4/CHF3 mixed gas was used for the primary etching and O2/N2 for CD/trench profile control, i.e. controlling the amount of polymer produced during etching process. As a result, a large amount of F- (high electro-negativity) dissociated from SF6, a serious side wall etching profile of silicon trench was observed, i.e. a worse CD control. (3) Cl2/CF4/CHF3 mixture was used as the major etching gas in the first etch step and NF3/Cl2/CF4/CHF3 mixture as the major etching gas in the second etch step. Then a vertical silicon trench profile is derived, leading to a possible process in manufacturing high density 4F2 array transistor.

章節目錄
致謝辭..............................................................................................................................II
摘要.................................................................................................................................III
Abstract ..........................................................................................................................IV
章節目錄..........................................................................................................................V
圖目錄............................................................................................................................VI
表目錄..........................................................................................................................VIII
第一章 緒論....................................................................................................................1
1.1 研究背景……………………………………………………………………………………………………..1
1.2 研究方向………………………………………………………………………………………………………1
第二章 文獻回顧............................................................................................................2
2.1 現行DRAM製程的主要結構………………………………………………………………………..2
2.2 DRAM各世代的發展比較………………………………………………………………………………3
2.3 垂直式電晶體與其電性上的優異表現……………………………………………………..…5
2.4 垂直式電晶體之結構……………………………………………………………………………………6
2.5半導體電漿蝕刻技術…………………………………………………………………………………….7
2.5.1何謂電漿…………………………………………………………………………………………………8
2.5.2如何產生電漿………………………………………………………………………………………….8
2.5.3電漿中的碰撞………………………………………………………………………………………….9
2.5.4 蝕刻製程參數之影響………………………………………………………………………….11
2.5.5 電漿蝕刻反應流程………………………………………………………………………………11
2.5.6 高密度低工作壓力(High ensity low pressure,HDLP)的電漿系統……….12
2.5.7 蝕刻氣體與參數間的影響研究與討論……………………………………………….13
2.5.8 聚合物或側壁沉積物的化學結構……………………………………………………….14
第三章 實驗流程與方法..............................................................................................16
3.1 試片製作流程…………………………………………………………………………………………….16
3.2 實驗流程說明…………………………………………………………………………………………….17
3.3 實驗相關條件……………………………………………………………………………………………19
3.3.1 實驗光罩設計與線寬…………………………………………………………………………19
3.3.2 蝕刻目標………………………………………………………………………………………………19
3.4 實驗設備簡介…………………………………………………………………………………………….19
3.4.1 浸潤式曝光機………………………………………………………………………………………19
3.4.2 乾蝕刻機………………………………………………………………………………………………20
3.4.3 掃描式電子顯微鏡………………………………………………………………………………21
第四章 實驗結果與討論..............................................................................................25
4.1 抗反射層與非晶質碳蝕刻實驗結果………………………………………………………….25
4.2 碳蝕刻相關數據收集…………………………………………………………………………………28
4.3 氮化矽(Si3N4)乾蝕刻…………………………………………………………………………………31
4.4 單晶矽淺溝槽乾蝕刻…………………………………………………………………………………32
4.4.1 簡單氣體組合對矽淺溝槽之影響研究與討論……………………………………33
4.4.2 使用複雜氣體組合對矽淺溝槽之影響研究與討論………………………......39
4.4.3 複雜氣體與多步驟蝕刻對矽淺溝槽之影響研究與討論………………….48
第五章 結論..................................................................................................................56
參考文獻…………………………………………………………………………………………………………………..58

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