臺灣博碩士論文加值系統

本論文提出了四種適用於可攜式裝置之參考電壓電路設計，擺脫過往使用BJT電晶體來實施負溫度係數，本論文組合了MOS電晶體偏壓於弱反轉區時所具有的正溫度係數電壓，與電晶體臨界電壓所具有的負溫度係數特性，計算出適合權重的比例後再予以互相抵消，以達成零溫度係數之輸出電壓。

本研究使用TSMC 0.18微米製程參數進行佈局及實作，並使用 HSPICE電路模擬軟體執行佈局前、後模擬；提出的四種電路中，前兩種電路是在負責提供負溫度係數的MOS電晶體上再串連一個P型及N型的電晶體，後兩種電路則是在按照尺寸比產生正溫度係數的電晶體與接地間分別連接一個P型及N型的電晶體，藉此產生適當的偏壓以及具有零溫度係數的參考電壓。

根據佈局前模擬結果，供應電壓皆為1.8V，輸入電壓從0.39V到0.45V不等，觀察的溫度變化皆由－20oC到120oC，佈局結果顯示，N型改良電路的輸出電壓差異量比P型改良電路來得較小，且四種電路的消耗功率都控制10毫瓦以內，由此可知，模擬結果與理論推導皆相符合，也證明了本論文的可行性。本論文所提出適用於可攜式裝置之參考電壓電路可適用於各種相關之類比積體電路設計與可攜式電子裝置。

This paper has proposed four different reference voltage circuits which are suitable for portable devices. Without using BJT transistors to implement both negative temperature-coefficients and positive temperature- coefficient voltages, instead, MOS transistors have been applied to all the proposed circuits. Properly biased the MOSFET in weak-inversion region, both the positive and negative temperature-coefficients parameters can be obtained. After choosing appropriate weightings, a zero temperature-coefficient reference voltage can be realized.

In the studies, all the proposed circuits use TSMC 0.18 m process parameters to make the layout and taped-out. HSPICE circuit simulation program has been used to perform pre- and post-layout simulations. The first two circuits are connected in series with a NMOS and/or PMOS transistor that is used for providing the negative temperature-coefficient voltage. For the latter two circuits, a P-type transistor and an N-type transistor is connected between the transistors that used to generates the positive temperature coefficient and ground, respectively.

According to the pre-layout simulation results, when the supply voltage is 1.8V, the bias voltage varies from 0.39V to 0.45V, and the temperature changes from -20oC to 120oC, the variation of the output voltage of the N-type modified circuit is lower than the P-type one. The proposed circuit is simple, and the power consumption of all the four circuits is less than 10 mW. From the simulation results, it can be seen that the simulation results are consistent with the theoretical derivation, which also proves the feasibility of the design principle. The reference voltage circuits proposed in this paper can be applied to various related analog integrated circuits and other portable devices.

摘要..........................i
Abstract..........................ii
誌謝..........................iii
目錄..........................iv
表目錄..........................vi
圖目錄..........................vii
符號說明 ..........................ix
第一章 緒論..........................1
1.1 積體電路發展沿革..........................1
1.2 設計流程..........................2
1.3 研究方向與重點..........................3
1.4 論文架構簡介..........................3
第二章 參考電壓回顧..........................4
2.1 參考電壓介紹..........................4
2.2 參考電壓電路架構與工作原理..........................4
2.2.1 BJT參考電壓電路..........................5
2.2.2 利用MOSFET實現參考電壓電路..........................10
第三章 四種適用於可攜式裝置之改良參考電壓電路..........................13
3.1第一種改良電路..........................13
3.1.1 電路工作原理..........................14
3.1.2 電路佈局前模擬結果..........................15
3.2第二種改良電路..........................18
3.2.1電路工作原理..........................18
3.2.2 電路佈局前模擬結果..........................19
3.3 第三種改良電路..........................21
3.3.1 電路工作原理..........................21
3.3.2 電路佈局前模擬結果..........................22
3.4第四種改良電路..........................23
3.4.1 電路工作原理..........................24
3.4.2 電路佈局前模擬結果..........................25
第四章 佈局後模擬結果..........................28
4.1 晶片設計流程..........................28
4.2.1第一種改良式參考電壓電路..........................31
4.2.2 第二種改良式參考電壓電路..........................35
4.2.3第三種改良式參考電壓電路..........................39
4.2.4第四種改良式參考電壓電路..........................43
第五章 晶片量測結果與實體圖..........................48
5.1 電路晶片實現與晶片量測結果..........................48
5.1.1 第一種改良參考電壓電路..........................49
5.1.2 第二種改良參考電壓電路..........................53
5.1.3 第三種改良參考電壓電路..........................55
5.1.4 第四種改良參考電壓電路..........................57
第六章 結論..........................61
參考文獻..........................62
Extended Abstract..........................65

[1]Neil H.E Weste, David Harris，柯鴻禧、黃琪聰(譯)，“COMS積體電路設計概論”，台灣培生教育出版股份有限公司，2007。
[2]謝永瑞，“VLSI概論(修訂四版)”，全華科技圖書股份有限公司，2008。
[3]高德遠、康繼昌，“VLSI-系統和電路的設計原理”，儒林圖書有限公司，1992。
[4]D. F. Hilbiber, “A New Developments in IC Voltage Regulators”, IEEE International Solid-State Circuits Conference, vol. VII, pp. 32-33, Feb. 1964.
[5]R. J. Widlar, “New Developments in IC Voltage Regulators”, IEEE International Solid-State Circuits Conference, vol. XIII, pp. 158-159, Feb. 1970.
[6]K. E. Kuijk, “A Precision Reference Voltage Source” IEEE International Solid-State Circuits Conference, vol. 8, pp. 222-226, June 1973..
[7]汪天心，“改良式低功率參考電壓設計”，國立虎尾科技大學電子工程系研究所碩士論文，2017年，7月。
[8]Wei-Bin Yang, Horng-Yuan Shih , Yu-Yao Lin, Ming-Hao Hong, Chi-Hsiung Wang, and Yu-Lung Lo, “A 1.8-V 4.36-ppm/°C-TC bandgap reference with temperature variation calibration”, 2013 International SoC Design Conference, pp. 103-106, 2013..
[9]Min Tan, Fan Liu, and Fei Xiang, “A novel sub-1-V bandgap reference in 0.18µm CMOS technology”, 2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification, pp. 180-183, 2011.
[10]E. K. F. Lee, “A low voltage CMOS bandgap reference without using an opamp” , 2009 IEEE International Symposium on Circuits and Systems, pp. 2533-2536, 2009.
[11]P. E. Allen and D. R. Holberg, “CMOS Analog Circuit Design”, Qxford University Press, Second Edition, 2002.
[12]陳郡豪， “工作於次臨界區本體推動之低電壓低電流微型運算放大器”，國立聯合大學電子工程研究所碩士論文，2006。
[13]施家豪， “低功率參考電壓設計”，國立虎尾科技大學電子工程研究所碩士論文，2013年，7月
[14]Y. P. Tsividis and R. W. Ulmer, “A CMOS voltage reference”, IEEE J. Solid-State Circuits, vol. SC-13, pp. 774-778, Dec. 1978.
[15]G. Giustolisi, G. Palumbo, M. Criscione, and F. Cutrì, “A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs”, IEEE Journal of Solid State Circuits, vol. 38, No.1, pp. 151-154, Jan. 2003.
[16]Chia-Wei Chang, Tien-Yu Lo, Chia-Min Chen, Kuo-Hsi Wu, and Chung-Chih Hung, “A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation”, 2007 IEEE International Symposium on Circuits and Systems, pp. 3844-3847, 2007.
[17]M. H. Cheng, and Z.W. Wu, “Low-power low-voltage reference using peaking current mirror circuit”, ELECTRONICS LETTERS, vol. 41, No. 10, pp. 572-573, May, 2005.
[18]P. R. Gray, P. J. Hurst, H. Lewis, and R. G. Meter, “Analysis and design of analog integrated circuits”, New York, John Wiley & Sons, Inc. 4th edition, 2001
[19]Jianping Wang, Xinquan Lai, Yushan Li, Jie Zhang, and Xiaofeng Guo, “A novel low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs”, 2005 6th International Conference On ASIC, vol. 1, pp. 369-373, 2005.
[20]Jun He, Degang Chen, and R. Geiger, “Systematic characterization of subthreshold-mosfets-based voltage references for ultra low power low voltage applications”, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, pp. 280-283, 2010.
[21]Yilei Li, Yu Wang, Na Yan, Xi Tan, and Hao Min, “A subthreshold MOSFET bandgap reference with ultra-low power supply voltage”, 2011 IEEE 9th International Conference on ASIC, pp. 862-865, 2011.
[22]O. E. Mattia, H. Klimach, and S. Bampi “0.9 V, 5 nW, 9 ppm/oC resistorless sub-bandgap Voltage reference in 0.18μm CMOS”, 2014 IEEE 5th Latin American Symposium on Circuits and Systems, pp. 1-4, 2014.
[23]Jianping Wang, Xinquan Lai, Yushan Li, Jie Zhang, and Xiaofeng Guo, “A novel low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs”, 2005 6th International Conference On ASIC, vol. 1, pp. 369-373, 2005.
[24]S. Ramasamy, B. Venkataramani, P. Meenatchisundaram, “A low power CMOS voltage reference circuit with subthreshold MOSFETs”, 2008 International Conference on Electronic Design, pp. 1-6, 2008.
[25]Jun He, Degang Chen, and R. Geiger, “Systematic characterization of subthreshold-mosfets-based voltage references for ultra low power low voltage applications”, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, pp. 280-283, 2010.
[26]I. Fakharyan and M. Ehsanian “A sub-1V nanowatt CMOS bandgap voltage reference with temperature coefficient of 13ppm/°C”, 2015 23rd Iranian Conference on Electrical Engineering, pp. 1129-1132, 2015.