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The purpose of this study is to analyze and improve thin wafer chip bonding operation in the Chip on Wafer process. In this operation, wafer warpage can cause adverse effects such as inability to pick up the wafer, difficulty in controlling the flatness of the wafer during wafer bonding, and electrical failure due to bump cracks within the wafer after bonding. Therefore, this study uses the Taguchi method to derermine the optimal parameter combination to minimize wafer warpage in the Chip on Wafer process of a case company. In this study, three factors affecting the amount of warpage are considered including increasing silicon wafer, polyimide and Nitride thickness. Each factor is given two levels and the experiments are performed according to an L8 orthogonal array. The amount of warpage is measured by TSM (Thermal Shadow Moiré). Then the S/N ratio is calculated to find out the optimal parameter combination. Finally, the parameter combination of the minimum warpage is applied to the actual wafer bonding operation for verification. The verification result shows that the electrical test yield of this combination is 68.7%, which is indeed higher than other combinations in the original orthogonal array.
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