臺灣博碩士論文加值系統

本論文提出一個應用於 SATA III 的展頻時脈產生器，以三角波做為調變波形之三角積分調變器為基礎，加上相位補償的技巧以產生真實的分數除數，減低三角積分調變的量化誤差。電路中的多相位時脈使用低頻的延遲鎖定迴路來產生，達到節省功耗以及面積的目標。本論文解決了平均分數除數在展頻功能開啟時，由於量化誤差造成頻譜能量不平均，造成電磁干擾抑制量不佳的問題。使用台積電 0.18μm 1P6M 製程製作晶片，核心電路的面積為 0.48×0.39mm2。輸出時脈的基礎頻率為 6GHz，展頻功能開啟後，向下展頻 5000ppm，頻譜能量分佈於 5.97GHz 到 6GHz 之間，電壓源為 1.8V，模擬結果顯示核心電路的總功耗為 24.7mW，電磁干擾抑制為 22.02dB。

This paper proposes a spread-spectrum clock generator (SSCG) that can be applied to SATA III. It is based on a delta-sigma modulator (DSM) with triangular wave as modulation profile. The phase compensation technique is used to generate true fractional divisor and reduce the quantization error. The multiphase clock in the circuit is generated using a low frequency delay-locked loop (DLL) to achieve power and area savings. This work solves the problem that spectrum is not even in SSC-ON mode if average fractional divisor is used. Average fractional divisor causes larger quantization error and results in poor electromagnetic interference (EMI) reduction. The chip is fabricated in TSMC 0.18μm 1P6M process, and core area is only 0.48×0.39mm2. The fundamental frequency of the output clock is 6GHz. When SSC is turned on, the frequency spreads down 5000ppm and the spectrum is distributed between 5.97GHz and 6GHz. The power supply is 1.8V and the power dissipation is 24.7mW. EMI reduction is 22.02dB.

第1章 緒論 12
1.1 研究動機與目的 12
1.2 論文章節架構 15
第2章 展頻時脈產生器先前技術探討 16
2.1 電磁波干擾與解決方法 16
2.2 展頻時脈概念 16
2.3 基本分數型鎖相迴路 20
2.4 三角積分調變技術 21
2.5 相位補償技術 24
2.6 相關先前技術 27
第3章 展頻時脈產生器電路設計 30
3.1 SATA III規格介紹 30
3.2 本論文設計概觀 32
3.3 本文展頻操作說明 34
3.4 相位頻率偵測器(Phase Frequency Detector, PFD) 37
3.5 充電泵與共模迴授(Differerential Charge Pump with CMFB)[14] 39
3.6 低通濾波器(Low Pass Filter, LPF)[14] 45
3.7 全差動電壓控制振盪器(Fully Differential VCO)[14] 48
3.8 高壓電路產生器(High Voltage Generator, HVG)[14] 57
3.9 參考電壓源、電流源(Voltage Reference & Current Reference) 61
3.10 預除器 (Prescaler)[14] 66
3.11 50% 責任週期除 3 電路 (50% Duty Divider By 3) 69
3.12 延遲鎖定迴路 (Delay Locked Loop, DLL) 70
3.13 三角波產生器 (Triangular Wave Generator) 75
3.14 上/下計數器(up/down counter) 77
3.15 4對 16 解碼器 (4x16 Decoder) 78
3.16 相位選擇器 (Phase Selector) 80
3.17 三角積分調變器 (Delta−Sigma Modulator) 81
第4章 電路佈局模擬 88
4.1 系統驗證 88
4.2 展頻時脈產生器電路佈局 96
4.3 展頻時脈產生器佈局後模擬 104
4.4 佈局應注意之細節 108
4.5 文獻比較 112
第5章 結論與未來研究方向 113
5.1 結論 113
5.2 未來研究方向 113
參考文獻 115

[1] H.-R. Lee, O. Kim, G. Ahn, and D. K. Jeong, “A Low Jitter 5000 ppm Spread Spectrum Clock Generator for Multi-channel SATA Transceiver in 0.18um CMOS,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, pp. 160–161, 2005.
[2] M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T. Hayasaka, T. Takahashi, and J. Kasai, “Spread-Spectrum Clock Generator for Serial ATA Using Fractional PLL Controlled by Δ∑ Modulator with Level Shifter,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, pp. 160–590, 2005.
[3] D.-S. Shen and S.-I. Liu, “A Low-Jitter Spread Spectrum Clock Generator Using FDMP,” IEEE Tran. on Circuits And Systems II, vol. 54, no. 11, pp. 979–983, Nov. 2007.
[4] S.-Y. Lin and S.-I. Liu, “A 1.5 GHz all-digital spread-spectrum clock generator,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3111–3119, Nov. 2009.
[5] C.-Y. Yang, C.-H. Chang, and W.-G. Wong, “A Δ-∑ PLL-based spread spectrum clock generator with a ditherless fractional topology,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 1, pp. 51–59, Jan. 2009.
[6] Y.-H. Kao and Y.-B. Hsieh, “A low-power and high-precision spread spectrum clock generator for serial advanced technology attachment applications using two-point modulation,” IEEE Trans. Electromagn. Compat., vol. 51, no. 2, pp. 245–254, May 2009.
[7] D. D. Caro, C. A. Romani, N. Petra, A. G. M. Strollo, and C. Parrella, “A 1.27 GHz, all-digital spread spectrum clock generator/synthesizer in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1048–1060, May 2010.
[8] W.G. Wong, “A Spread-Spectrum Clock Generator Using a Phase-Compensation Fractional Phase-Locked Loop Technique”, National Chung Hsing University, 2006.
[9] K.-H. Cheng, C.-L. Hung, and C.-H. Chang, “A 0.77 ps RMS jitter 6-GHz spread-spectrum clock generator using a compensated phaserotating technique,” IEEE J. Solid-State Circuits, vol. 46, no. 5, pp. 1198–1213, May 2011.
[10] S. Hwang, M. Song, Y.-H. Kwak, I. Jung, and C. Kim, “A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile,” IEEE J. Solid-State Circuits, vol. 47, no. 5, pp. 1199–1208, May 2012.
[11] C.-H. Weng and T.-C. Lee, “A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 5, pp. 1264–1273, May 2013.
[12] M. Song, S. Ahn, I. Jung, Y. Kim, and C. Kim, “Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation,” IEEE Trans. VLSI Syst., pp. 1234–1245, July. 2013.
[13] T.-H. Lin and Y.-J. Lai, “An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 340–349, Feb. 2007.
[14] Z.X. Yang “Low-Power 6-G bit/s Spread Spectrum Clock Generator with Process Compensation Scheme,” National Taipei University. Electrical Engineering, 2014.
[15] C.Y. Hsu “A 6-G bit/s SATA Spread-Spectrum Clock Generator,” National Taipei University. Electrical Engineering, 2009.
[16]J. Zhou and W. Dehaene, “A synchronization-free spread spectrum clock generation technique for automotive applications,” IEEE Trans. Electromagn. Compat., vol. 53, no. 1, pp. 169–177, Feb. 2011.
[17]I. T. Lee, S. H. Ku, and S. I. Liu, “An all-digital spread spectrum clock generator with self-calibrated bandwidth,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 11, pp. 2813–2822, Nov. 2013.
[18]T. Kawamoto, M. Suzuki, and T. Noto, “1.9-ps jitter, 10.0 dBm EMI reduction spread-spectrum clock generator with autocalibration VCO technique for serial-ATA application,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 5, pp. 1118–1126, May 2014.
[19]H.-H. Chang, I.-H. Hua, and S.-I. Liu, “A Spread-Spectrum Clock Generator with Triangular Modulation,” IEEE J. Solid-State Circuits, vol.30, no. 4, pp. 673–676, Apr. 2003.
[20] B. Miller and R. J. Conley, “A Multiple Modulator Fractional Divider, IEEE Transactions on Instrumentation and Measurement,” vol. 40, no. 3, June 1991.
[21] K.-B. Hardin, J.-T. Fessler, and D.-R. Bush, “Spread Spectrum Clock Generation for The Reduction of Radiated Emissions,” in IEEE Int. Symposium on Electromagnetic Compatibility Conf. Tech. Papers, pp. 227–231, 1994.
[22] L. W. Couch II, “Digital and Analog Communication Systems,” Macmillan, 1987.
[23] S.-I. Liu and C.-Y. Yang , “A Phase Locking Loop,” Tsang Hai, 2006.
[24] I.-A. Young, J.-K. Greason, J.-E. Smith, and K.-L.Wong, “A PLL Clock Generator with 5 to 110-MHz of Lock Range for Microprocessors,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, pp. 0-51, 1992.
[25] B. Razavi, “Design of Analog CMOS Integrated Circuits,” 1ST ED., McGraw-Hill, 2001.
[26] Y.-H. Chuang, S.-L. Jang, J.-F. Lee, and S.-H. Lee, “A Low Voltage 900-MHz Voltage Controlled Ring Oscillator With Wide Liming,” in IEEE Asia-Pacific Conf. on Circuits and Systems Tech. Papers, pp. 301–304, 2004.
[27] J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, and M. Shankaradas, “Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock-Generator PLL,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, 2003.
[28] C.-Y. Yang, J.-W. Chen, Meng-Ting Tsai, “A High-Frequency Phase-Compensation Fraction-N Frequency Synthesizer,” IEEE International Symposium on Circuits and Systems, May. 2005.
[29] R. Woogeun and A. Akbar, “An on-chip phase compensation technique in fractional-N frequency synthesis,” IEEE Proceedings of ISCAS, 1999.
[30] Y.-C. Huang, M.-D. Ker and C.-Y Lin, “ Design of Negative High Voltage Generator for Biphasic Stimulator with SoC Integration Consideration,” in Proc. IEEE BioCAS 2012, pp. 28-30, 2012.
[31] J. Kim, P. K. T. Mok, and C. Kim, “A 0.15 V input energy harvesting charge pump with dynamic body biasing and adaptive dead-time for efficiency improvement,” IEEE J. Solid-State Circuits, vol. PP50, no. 2, pp. 414–425,Feb. 2015.
[32]Q. Duan and J. Roh, “A 1.2-V 4.2-ppmoc high-order curvaturecompensated CMOS bandgap reference,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 3, pp. 662–670, Mar. 2015.
[33] F. Serra-Graells , "Sub-1-V CMOS Proportional-to-Absolute Temperature references", IEEE J. Solid-State Circuits , vol. 38 , no. 1 , pp.84 -88 , 2003.
[34] C.-Y. Chu and Y.-J. Wang, “A PVT-independent constant- gm bias technique based on analog computation,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 10, pp. 768–772, Oct. 2014.
[35] W. M. Sansen , F. O. Eynde and M. Steyaert , "A CMOS temperature-compensated current reference", IEEE J. Solid-State Circuits , vol. 23 , no. 3 , pp.821 -824 , 1988.
[36] H. J. Oguey and D. Aebischer , "CMOS current reference without resistance", IEEE J. Solid-State Circuits , vol. 32 , no. 7 , pp.1132 -1135 , 1997.
[37] G. Serrano and P. Hasler , "A precision low-TC wide-range CMOS current reference" , IEEE J. Solid-StateCircuits , vol. 43 , no. 2 , pp.558 -565 , 2008.
[38] K. Ueno , "A 300 nW 15 ppm CMOS voltage reference circuit consisting of sub-threshold MOSFETs" , IEEE J. Solid-State Circuits , vol. 44 , no. 7 , pp.2047-2054 , 2009.
[39] A. M. Pappu , X. Zhang , A. V. Harrison and A. Apel , "Process-invariant current source design: Methodology and examples" ,IEEE J. Solid-State Circuits , vol. 42 , no. 10 , pp.2293 -2302 , 2007.
[40] M. Choi, I. Lee, T.-K. Jang, D. Blaauw, and D. Sylvester, “A 23 pW, 780 ppm/oc resistor-less current reference using subthreshold MOSFETs,” in Proc. Eur. Solid State Circuits 40th Conf. (ESSCIRC 2014), pp. 119–122,Sep. 2014.
[41]J. Lee and S. Cho, “A 1.4-μW 24.9-ppm/°C current reference with process-insensitive temperature compensation in 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2527–2533, Oct. 2012.
[42] R. Mohanavelu and P. Heydari, “A Novel 40-GHz Flip-Flop-Based Frequency Divider in 0.18-um CMOS,” in IEEE European Solid-State Circuits Conf. Tech. Papers, pp. 185–188, 2005.
[43] J.P.A. van der Wagt, G.G. Chu and C.L. Conrad, "A layout structure for matching many integrated resistors ,"IEEE Trans. Circuits and System, vol.51, no.1, pp. 186- 190, Jan. 2004.
[44] J. D. Bruce, H. W. Li, M. J. Dallabatta, and R. J. Baker, "Analog layout using ALAS!," IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 271-274, Feb. 1996.